I didn't see any pins for RTS or CTS here, but is UART flow control supported?

Hi,
Why are there no voltage constraints specified in this file?

Thanks!

Those options have been already added for Nexys Video (see the commit by @bg2d).

When these options are left unset, the Vivado Design Suite reports an implementation warning:

[DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND

set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.

As I understand it, the Arty-A7 35 and 100 boards are pin-compatible, so the xdc files should look exactly the same. A quick inspection shows that the only difference (apart from formatting) is in the section ChipKit Inner Analog Header - as Digital I/O where pins are named differently.

I would propose to merge these two files to avoid confusion.

Environment

• Windows 10 pro v1909
• Vivado v2019.1 (and XSDK)
• Cora Z7 (Z7-07S)

I am working with the Vivado and XSDK application using Cora Z7 (Z7-07S).
I use Pmod JA and Pmod JB pins for UARTLite (1 + 4 UARTs).

I used Master XDC files (Cora-Z7-07S.xdc) from this site. However, concerning the Pmod JB pins, the assignment seems reversed.

To be more specific:

jb[0] and jb[1] are connected to the "4th" UART (Pmod JB pin 6 and 7)
jb[2] and jb[3] are connected to the "3th" UART (Pmod JB pin 4 and 5)
jb[4] and jb[5] are connected to the "2th" UART (Pmod JB pin 2 and 3) 
jb[6] and jb[7] are connected to the "1th" UART (Pmod JB pin 0 and 1) 

Concerning the Pmod JA pins, there is no such problem.

Pmod JB pin assignment seems strange.

Appendix

I checekd Vivado Block design and the assignments in the XSDK several times finding no mistakes (probably).

/* Definitions for peripheral AXI_UARTLITE_1 */
#define XPAR_AXI_UARTLITE_1_BASEADDR 0x40610000
#define XPAR_AXI_UARTLITE_1_HIGHADDR 0x4061FFFF
#define XPAR_AXI_UARTLITE_1_DEVICE_ID 1
#define XPAR_AXI_UARTLITE_1_BAUDRATE 9600
#define XPAR_AXI_UARTLITE_1_USE_PARITY 0
#define XPAR_AXI_UARTLITE_1_ODD_PARITY 0
#define XPAR_AXI_UARTLITE_1_DATA_BITS 8

/* Definitions for peripheral AXI_UARTLITE_2 */
#define XPAR_AXI_UARTLITE_2_BASEADDR 0x40620000
#define XPAR_AXI_UARTLITE_2_HIGHADDR 0x4062FFFF
#define XPAR_AXI_UARTLITE_2_DEVICE_ID 2
#define XPAR_AXI_UARTLITE_2_BAUDRATE 9600
#define XPAR_AXI_UARTLITE_2_USE_PARITY 0
#define XPAR_AXI_UARTLITE_2_ODD_PARITY 0
#define XPAR_AXI_UARTLITE_2_DATA_BITS 8

...

The ja, jb, jc, jd of genesys2 are not the same as the document

Extra bracket on line 89-
[current_design]] --> [current_design]

Causes 'Invalid option value' critical warning

Hi,

I noticed wrong pins in master xdc file for

https://github.com/Digilent/digilent-xdc/blob/master/Arty-Z7-10-Master.xdc

## ChipKit Inner Analog Header - as Digital I/O
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L1N_T0_AD0N_35       Sch=AD0_N
#set_property -dict { PACKAGE_PIN C20   IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L1P_T0_AD0P_35       Sch=AD0_P
#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N
#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P
#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2N_T0_AD8N_35       Sch=AD8_N
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P

According to schematics file
https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty_z7_sch.pdf

should be
a6 -> ad12_p -> PACKAGE_PIN F19
a7 -> ad12_n -> PACKAGE_PIN F20
a8 -> ad0_p -> PACKAGE_PIN C20
a9 -> ad0_n -> PACKAGE_PIN B20
a10-> ad8_p -> PACKAGE_PIN B19
a11-> ad8_n -> PACKAGE_PIN A20

Can you please verify this?

Thank you

I want to use the pins IO13-IO10 and IO39-IO36 as I/O but only half of the pins are declared.Also how do I set VCC and GND on pins?

Hi guys There is TYPO in head of cora z7-10 xdc - there is text: ## This file is a general .xdc for the Cora Z7-07S Rev. B

but it should correspond with cora z7-10 Rev. XX

Why such as nexys4-ddr xdc file doesn't have ddr pin . how can i use it?

Vivado is giving warnings for this. Not sure if it's an error or a hardware design.

From Nexys-A7-100T-Master.xdc:

##Switches
#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
#set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]

The Basys 3 and Nexys 4 use set_property twice per port, rather than using -dict to set both IOSTANDARD and PACKAGE_PIN in the same line

Pins J17 is connected to txd in the .xml for the board, and j18 connected to rxd, however in the xdc file they are swapped.

I'd like to use some of these files (the XDC of the Arty Z7-20 in particular) in some of my open source projects, but they don't have any copyright statement in them. Could you add a copyright statement to these file?
Christopher

Receive port must be named as input and transmit port must be named as output.

Now:
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in

Correct:
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_in }]; #IO_25_14 Sch=uart_rxd_in
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_out }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_out