dinyar / ugmtfirmware Goto Github PK

Currently there are two modules with almost identical functionality for the first sort stage and one module with very similar functionality for the second sort stage.

These should be merged into one if possible. The same applies for the "count_wins" function. It is implemented in 4 different versions with almost identical functionality.

Currently the isolation is assigned to all final muons, i.e. also to those that are actually empty. This leads to output muons with all-zero values except for isolation.

The muons coming from the positive and negative side of the overlap and forward regions are swapped in the sorter unit. This leads to inconsistencies with the emulator and should be changed.

I assume the emulator orders the intermediate muons the "usual" way, i.e. FWD+ OVL+ BRL OVL- FWD- while the firmware currently orders these FWD OVL BRL. This should be adjusted.

Currently coordinate-based ghost busting is broken as it implicitly expects absolute coordinates, but doesn't handle wrap-around. We should find out whether we will receive relative or absolute coordinates and then implement the unit accordingly.

Currently the valid bit is set per muon. This leads to problems when assigning the valid bit to output energy sums and extrapolated coordinates. It also may produce problems with synchronisation. It should therefore be set per bunch crossing.

Currently the testbench ignores the isolation bits. This should be changed.

The calo output (links 15-26) have valid bit set to 0.

The serializer stage swallows the first 32 bit word of each bunch crossing.

In case of a tie between two muons in the final sorter the one with the higher index wins within a track finder. This should be reversed. The muon with the lower index (i.e. the one sorted first in the stage before) should win.

The testbench written for #1 should include both the sort rank and empty bit of a muon when it is dumped to the command line. This should make debugging easier.

Currently the testbench for the sort and cancel unit is rather messy. It should be refactored to clean up the output, all inputs have to be properly reset in the beginning. Furthermore all duplicate code has to be factored out into procedures.

During the automatic checking the serializer testbench should output more detailed errors in the event of an error, similar to what was implemented in #25. This would mean to show (at least) the mismatched frame and what was expected, but maybe also the frames +/-1.

In the serializer testbench the outputs are not read correctly as the process doing this is run only after the serializer has completed processing.

The delay line in the serializer for the intermediate muons is currently broken. This leads to them being sent right away instead of one BX later.

The absolute isolation LUT is very small (actually only a 32 bit word). While there are only 8 of these it is a waste to use bRAMs. We should switch to distributed RAM for that reason.

In the single muon test pattern (see http://goo.gl/J76GzT) the "best" muon is sent on the third position if the two null-frames are taken as reference for the first position. It should be on second position however.

Currently both the isolation bits as well as the final muons are registered in the ugmt serdes module while the debugging outputs (intermediates, extrapolated coordinates and final energies) are not. This should be fixed in the spirit of consistency. (They are delayed by one additional bx in the sorter unit for this reason.)

Using the single mu pattern file (found at http://goo.gl/dt3iXj) the second word of each final muon is sent to early when going through either the endcap or overlap sorter.

This does not show with the single tf pattern file for some reason.

The extrapolation and isolation LUTs are currently empty. This makes them output 'U' in simulation and '0' in hardware. At the latest before testing the isolation logic they should be filled with defined data.

The isolation LUT vhd file should be added to the dep file. In this way it is automatically added to the project and also available in simulation.

In the newest version (ugmt_v0_2_0), the intermediate muons and ranks come 6 frames earlier w.r.t. the first final muon.

The table summarizing all LUTs is severely out of date. This should be updated before we start testing IPbus.

Currently we set the data valid bit for each word in a fixed structure: Positions 0 and 1 are always invalid while all others are always valid. This could break alignment of following cards and should thus be changed to propagate data valid state from downstream.

Currently the isolation assignment memories are implemented with inferred block RAMs, we should change this to generated RAMs as this turns out to be more efficient. We also have more control over the exact implementation that way. This is related to #6.

The sorting logic solves "draws" (equal sort ranks) by ranking the muon with the higher index higher. In the final sorter the index range has been inverted, so for draws sorting is inverted with regard to the first-level sorter. This is mainly a cosmetic problem, but should be fixed.

In the GMT module forward, respectively overlap muons from the negative and positive sides are merged into one vector. Here positive and negative sides are assigned in the wrong order.

Our custom ucf file(s) should be versioned.

Draw a diagram of the uGMT logic including all flip-flops etc.

The rewritten serializer stage sets the first four words invalid and only the last two valid. Actually the last four should be valid.

Currently only the final muons are registered in the GMT module while the intermediates are asynchronously propagated. To increase consistency this should be changed.

Currently the debugging outputs (muons and sort ranks) are not aligned with the final muons. At the moment it seems as though the 3rd muon is from the correct bx, but put into the slot for 1st muon, while 1st and second muon are shifted by one and are late by one bx.

Currently the debugging outputs for the isolation unit are not delayed. This should be changed to sync them with the final muons.

The testbench should dump the full event if an error is detected to ease debugging.

Still need to add the outputs for the debugging signals for the isolation module to the serialization stage.

This involves two steps:

• Actual code to add output links
• Modification of area constraints for serializer.

Via link 14 nothing is being sent. Is this on purpose?

Once the test pattern files include the output muons generated by the emulator (worked on in jlingema/uGMTScripts#10) the testbench can automatically check for correctness. This should be implemented in this issue.

Currently the intermediate results (muons and sort ranks) are delayed by 1 bx w.r.t. the final muons. This should be fixed.

The error count stated by the testbench is broken. Furthermore the output can be made more readable.

Can we do this without breaking timing?

The refactorings/bug fixes in #36 and #40 introduced small typos/omissions that led to the design not synthesising anymore. This is fixed here.

The serialization stage should be tested.

Currently the delay to sync the intermediate muons is placed in the GMT unit. This means that the testbench has to implement this delay again. Furthermore it is logically not optimal as this should be part of the sort and cancel unit.

In the newest version (ugmt_v0_2_0) all outputs (final, intermediate and ranks) seem to come 2 frames too late (i.e. not aligned with the 0vX 0vX 1vX 1vX 1vX 1vX pattern of the output muons)

We're not clear yet whether the first 32 bit word coming out of the inputs is delayed by a fixed number of 240 MHz clocks with regard to the 40 MHz LHC clock. (In simulations e.g. the delay is 3 clks after start of the simulations and 2 clks after sending a reset.)

There should be monitoring logic that detects when the valid bit transitions from low to high and counts how many have passed before this since clk40 went from low to high. (This happens once per orbit, not once per bunch crossing.)

Write a testbench that will only test the algorithm part, excluding the serdes stages.

In the deserialization stage the muons are filled in the wrong order. i.e. the first muon to arrive is put into the third bin while the first bin is filled with the third muon to arrive.

Currently a muon marked as empty (this happens when pT == 0 at the input) can cause another muon to be cancelled out. This can theoretically happen when the "empty" muon has pT == 0, but it's fields for eta, phi, and quality are set to some value. In this case the cancel-out unit would match it with a close-by muon and could then theoretically decide to cancel out the real muon.

Therefore the empty bit should be checked in the cancel-out units.

It looks like some entries are missing in the address table. Specifically, the rank-lut seems not to be there? Is it just missing in the repo or is it not hooked up to IPbus?