- Git
- Python3
- FPGA toolchain (direct link) ~100MB
- RISC-V toolchain ~220MB
- PyCharm ~450MB
- LiteX
- Rust
- ecpdap
wget https://github.com/open-tool-forge/fpga-toolchain/releases/download/nightly-20201214/fpga-toolchain-linux_x86_64-nightly-20201214.tar.xz
tar xf fpga-toolchain-linux_x86_64-nightly-20201214.tar.xz
PATH=$PATH:$(pwd)/fpga-toolchain/bin
wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14.tar.gz
tar xf riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14.tar.gz
PATH=$PATH:$(pwd)/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/binrustup default stable
rustup target add riscv32i-unknown-none-elfgit clone https://github.com/adamgreig/ecpdap
cd ecpdap
cargo install --path .
PATH=$PATH:$HOME/.cargo/binmkdir workspace
cd workspace
python3 -m venv .venv
source .venv/bin/activate
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
chmod +x litex_setup.py
./litex_setup.py init installcd litex-boards/litex_boards/targets/
./orangecrab.py --build
ecpdap program --freq=50000 build/orangecrab/gateware/orangecrab.bitCable Rx (white) -- FPGA Tx (1)
Cable Tx (green) -- FPGA Rx (0)
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads, dummy=6, endianness="little")
self.lxspi.add_clk_primitive(platform.device)
self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=16 * 1024 * 1024)
self.constants["FLASH_BOOT_ADDRESS"] = self.mem_map['spiflash'] + 0x00100000или
self.add_spi_flash(...)+update boot.c
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