djzenma / riscv-32ic-sim Goto Github PK

Add the following in the config file:

• Add Data Register File and Custom System Register File
• Add Operators based on data
• Create new instruction behavior based on the defined operators
• Add Custom Interupts given hardcoded interrupts (like NMI, TMR,...)

• Remove 'key:op' from instruction group level to 'primaryKey' being at the top level of all formats.
• Remove secondary and precedence and replace with concatenation in code.
• Fix Immediate Formats.

Simulator doesnt work on sample 6 and upwards

• Rename 'Name' to 'src' having as possible values either 'instr' or 'const'
  If 'const' then have a value field

• Support all possible architectures (16,32,...)

• Remove ImmediateLoadable

• If several architectures, must devine default architecture then foreach instruction that is not the default size, specify a mapping instr.