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LAP - Raytracing Hardware Accelerator for FPGA

Brief: Repository for the raytracing hardware accelerator designed for FPGAs in Chisel at the LAP - EPFL.

Content

This repository contains both the Chisel code for the Accelerator and the C++ code for modules generated using Vivado HLS.

This project was my Bachelor Thesis in 2019, and thus I've included the report of the thesis, along with the final presentation and the abstract.

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