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xv6-riscv undergrad projects for EEE3535 Operating Systems (2022-Fall Semester) @ Yonsei University

Makefile 2.17% C 94.41% Assembly 3.18% Perl 0.24%

demand-paging mlfq mlfq-scheduler operating-system operating-system-learning operating-systems-project os project ps shell syscall time tracker tracking university-project xv6 xv6-riscv

xv6-riscv-projects's Introduction

Joshua's Github

About Me

Name: Joshua Gabriel Dela Rosa
Based: Seoul, South Korea
Electrical and Electronics Engineering @ Yonsei
- Specializing in VLSI-Computer and Electrical Power Engineering
- Graduated Feb. 2024
Currently Interning at Computer Architecture and Systems Lab (CASL) @ Yonsei
Preparing for Graduate School @ Yonsei EEE (Fall 2024)
Resume

Some Projects

Researches

[Capstone Project] Harmonizing Grid Frequency: Investigating the Optimal Mix of Grid-Forming and Grid-Following Inverters in High Penetration Grids
[Communication Networks] Asynchronous VPPM VLC Algorithm

Recent Personal Projects

FPGA BASED Systolic Arrays (Planned for 2023-Winter)
- Output Stationary, Weight Stationary Implementations
- Scalable Systolic Array
- Implemented in PL, interfaced by PS

Boards

Raspberry Pi 4B
Arduino Uno
Arduino Nano
ESP32
Raspberry Pico
Xilinx PYNQ-Z2 FPGA Development Board
[NEW] Tang Nano 9k RISCV FPGA Development Board

Software

Xilinx Vivado, Xilinx Vitis
GPGPU-Sim
Accel-Sim
Chipyard
LTSpice, PSPice, HSpice
Logism
MATLAB
PowerWorld
PSCAD

xv6-riscv-projects's People

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