edaa-org / pysvmodel Goto Github PK

This repository and the matching Python package are now renamed.

At next, the banner should be updated to pySVModel.

There is work in progress in CHIPS Alliance to improve System Verilog support in open source tooling. The main parsers are verible and Surelog. The latter is tightly related to Universal Hardware Data Model (UHDM). There is also MikePopoloski/slang, which is being enhanced to generate UHDM.

Since Surelog and UHDM are written in C++, I asked @hzeller how might those be used from Python. He pointed me to UHDM.capnp interface, a serialized format that can be used from Python. See the dialogue: gitter.im/hdl/community?at=6148aed87cd57813a8d6270b. Therefore, it should be possible to plug pySVModel into UHDM, similarly to how we plug pyVHDLModel into pyGHDL.

Although working on this is not in the roadmap yet, I'm creating this issue as a placeholder/remainder.

/cc @mithro