Comments (1)
You can look at the user project example testbenches, the documentation can be found here.
from caravel_user_project.
Related Issues (20)
- user_project_wrapper must include standard cells HOT 1
- make setup error regaring environment variables HOT 1
- mpw-two-c to mpw-5b tags use picorv32 instead of vexRISC for simulation
- Cannot build macros on OpenLane tag `2023.02.14` HOT 4
- test-9a: Missing mag directory HOT 1
- File lock in magic during make ship HOT 2
- Wire user_proj_example.\wbs_dat_o is used but has no driver for example project itself
- Document how to update project HOT 2
- opensta failing on user_project_example HOT 1
- user_id_programming is flattened during synthesis HOT 2
- MPW tapeout repos do not always contain the tapeout data HOT 4
- The timing constraints are unnecessarily very aggressive.
- make setup error report
- Incorrect user_defines used in verification
- Routing congestion to high in user_project_wrapper
- Routing Congestion Heatmap Not Populated with Data HOT 13
- Running tests on Caravel's user_project_example does not work with the latest iVerilog release HOT 1
- facing issue in running cmd: make user_proj_example HOT 10
- make setup fails due to volare enable error HOT 1
- make setup fails with latest commit HOT 3
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from caravel_user_project.