Queries about litepcie about litepcie HOT 4 CLOSED

Hi @imBilal1998,

the documentation is indeed minimal for now (and we are going to improve this over time), but there are already several example of LitePCie integration on various boards:
-https://github.com/enjoy-digital/litepcie/tree/master/examples
-https://github.com/litex-hub/litex-boards/blob/master/README.md

Since LitePCIe currently relies on the integrated PCIe hard block of the supported devices, that's a requirement to get it working. Supporting others PCIe PHY would be possible but this is extra-work that has not been done yet (since we haven't had yet a use case for it).

A good board to start with LitePCIe is the Acorn CLE215+, the process to operate LitePCIe on is is explained in the target file:
https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/acorn_cle_215.py#L6-L21

Hoping it answers your questions,

Florent

from litepcie.

Thanks @enjoy-digital for such a quick reply. I would wish to keep this thread open for further queries for future users.

That very well answers my basic question. But can you tell me, on litepcie page getting started paragraph, What does the step 3 means?

Also that on the litepcie page. it is mentioned that LitePCIe can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core. How can I generate the verilog rtl? On litepcie phy folder some verilog files are provided? Is it the already generated verilog rtl?

Current I don't have Acorn CLE215 available and I am working on ZCU102 board. So I want to know, how much work is required to make PCIe run on this board? How can I manually integrate litepcie with ZCU102 board, given that it does not have any integrated block?

Thanks.

--Bilal

from litepcie.

The getting started is not yet written, the best for now is to look at the example design i was listing. You can use LitePCIe in a LiteX design by importing the LitePCIe core (full LiteX flow), but you can also generate a standalone LitePCIe core that you would just use as a verilog code in a traditional flow: for example in examples directory, you can generate a standalone core for the AC701 board with: litepcie_gen ac701.yml and then integrate in in your design using the corresponding provided .xci.

Regarding the ZCU102, it will provide the Physical Layer but the Data Link Layer will be missing since LitePCIe operates at the TLP layer, so it's possible, but would still requires some work (at least a few weeks full time for an experienced FPGA developer). If you want to work on this and contribute this, happy to help you and give directions, but otherwise, i would recommend using an FPGA with a PCIe hard block or use another core that would provide you all the layers (if available).

from litepcie.

Closing since the questions have been answered.

from litepcie.