Comments (4)
Hi @zhangzq71,
the current driver allocates the DMA buffers in litepcie_pci_probe
and then use this to configure the DMA descriptor on the hardware in litepcie_dma_writer_start
and litepcie_dma_reader_start
:
- https://github.com/enjoy-digital/litepcie/blob/master/litepcie/software/kernel/main.c#L237-L238
- https://github.com/enjoy-digital/litepcie/blob/master/litepcie/software/kernel/main.c#L288-L289
So currently the memory allocation is handled by the driver. If you want to do DMA on specific addresses, you'll need to program the DMA descriptors with a customized function.
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The DMAs in LitePCIe are generating/receiving streams of data (similar to AXI Streams). So on the FPGA side, there are no MMAP/destination address, we only have DMAs channels with data sink and source. If you want to also do MMAP on the FPGA, you then have to add a stream to/from MMAP DMA and configure it over PCIe. Such modules can be the WishboneDMAReader
/WishboneDMAWriter
from https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/dma.py if you want to do DMA on the main bus of the SoC, or LiteDRAMDMAReader``/LiteDRAMDMAWriter
from https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/dma.py if you want to do DMA directly to/from the DRAM memory.
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Related Issues (20)
- there is no packet separation capability for dma HOT 3
- flawed DMA driver HOT 1
- Is it ASIC proven? HOT 1
- CrossClockDomain FIFO depth too shallow causes inefficiencies HOT 1
- Compute Express Link (CXL) support HOT 2
- Support of Non-Transparent Bridge (NTB) for inter-domain communication through PCIe interfaces. HOT 3
- No Rx TLP with s7pciephy
- Problems with inter clock timing
- [NiteFury] Device not enumerating with x1 x2 HOT 4
- dma_test with external loopback HOT 1
- Implementing a versatile PCIe switch using LitePCIe HOT 1
- MSI stalls on Ultrascale+ HOT 2
- DMA prog mode status register race condition / early-update HOT 2
- [Feature request] Implementation of a Root Complex HOT 1
- DMAReader not working after update to 2023.12 HOT 8
- PCIe on UltraScalePlus with 256 bit width is broken HOT 4
- Expanding spiflash functionality in c++ driver with I2C bitbang and SPIMaster functions HOT 6
- The tlast signal doesn't seem to be working
- SIGKILL when doing a dma_test with zero-copy?
- how to generate the rtl code of crossbar and dma related .py
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