Comments (5)
I also just tried a x8
core with data_width=128
, this builds but the resulting bitstream crashes the whole host when trying to load the litepcie.ko
module.
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@smunaut: I just tested the BCU-1525 with a similar configuration and got it working. If would be interesting to see if the PCIe hardblocks are similar or different on these devices and if a specific adaptation could be required for the Zynq Ultrascale + PCIe hardblock.
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Mmm, AFAICT the ZU11EG
and the VU9P
both have the PCIE4
block and so should be identical :/
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Just in case, I was testing with a 200MHz sys_clk_freq
(it should not make a difference, but could be worth a try).
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PEBCAK
While changing the GTH Quad and regenerating the .xci appropriately, Vivado changed the "Request Completion Straddle" option to "True" which the adaptation layer to standard TLP can't deal with.
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Related Issues (20)
- litecpie dma test result in error HOT 3
- there is no packet separation capability for dma HOT 3
- flawed DMA driver HOT 1
- Is it ASIC proven? HOT 1
- CrossClockDomain FIFO depth too shallow causes inefficiencies HOT 1
- Compute Express Link (CXL) support HOT 2
- Support of Non-Transparent Bridge (NTB) for inter-domain communication through PCIe interfaces. HOT 3
- No Rx TLP with s7pciephy
- Problems with inter clock timing
- [NiteFury] Device not enumerating with x1 x2 HOT 4
- dma_test with external loopback HOT 1
- Implementing a versatile PCIe switch using LitePCIe HOT 1
- MSI stalls on Ultrascale+ HOT 2
- DMA prog mode status register race condition / early-update HOT 2
- [Feature request] Implementation of a Root Complex HOT 1
- DMAReader not working after update to 2023.12 HOT 8
- PCIe on UltraScalePlus with 256 bit width is broken HOT 4
- Expanding spiflash functionality in c++ driver with I2C bitbang and SPIMaster functions HOT 6
- clock domain separation of litepcie HOT 2
- kernel build result in error HOT 3
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