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ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)
cc: error: /usr/lib/armv7l-linux-gnu/libftdi.a: No such file or directory
cc: error: /usr/lib/armv7l-linux-gnu/libusb.a: No such file or directory
user wants to flash arbitrary binary to skip IDCODE check
intended use is ext3 linux filesystem to flash
but renaming to IMG didn't help
lawrie@lawrie-VirtualBox:~/SaxonSocDev/hardware/synthesis/ulx3s$ ujprog -j flash -f 0x100000 blink.img
ULX2S / ULX3S JTAG programmer v 3.0.92 (built Oct 21 2019 02:00:13)
Using USB cable: ULX3S FPGA 12K v3.0.3
Programming: 69% | double free or corruption (!prev)
Aborted (core dumped)
While adjusting some paths in the makefile is almost expected! I did have to modify the source to get it to compile at around line 824 of ujprog.c
//#ifdef __linux__
// usb_reset((void *) fc.usb_dev);
//#else
res = ftdi_usb_close(&fc);
in the makefile I had to comment out the arch define (the libs being in /usr/lib)
I had to add include directories
-I/usr/include/libftdi1 -I/usr/include/libusb-1.0
additionally I had to change the order of libs and add a few
FTLIB = /usr/lib/${ARCHNAME}/libftdi1.a
USBLIB = /usr/lib/${ARCHNAME}/libusb-1.0.a
ujprog: ${SRCS}
${CC} ${CFLAGS} ${SRCS} -o ujprog ${FTLIB} ${USBLIB} -lpthread -ludev
while specific lib name and path oddities are distro specific, maybe the source modification needs review ?
Hope this helps
Hi
I've seen that you also have some experience with the Flea Ohm board, as you are also using the FleaOhm JTAG tool (https://github.com/emard/FleaFPGA-JTAG).
Is it possible to make ujprog also compatible with the FleaOhm? That way a fully open source tool chain could be used with it. Currently Diamond is still necessary as Flea-Ohm-JTAG only flashes vme files.
I have tried to adapt the cable section by inserting:
{
.cable_hw = CABLE_HW_USB,
.usb_vid = 0x0403,
.usb_pid = 0x6015,
.cable_path = "FleaFPGA v2.5",
.tck = 0x08,
.tms = 0x04,
.tdi = 0x01,
.tdo = 0x02,
.cbus_led = 0x00
},
The board is then detected, but the JTAG chain does not seem to work:
$ ./ujprog -d -b115200 ../../../../FleaFPGA-Ohm/FleaFPGA_Ohm_test/impl1/Blinky_impl1.bit
ULX2S / ULX3S JTAG programmer v 3.0.92 (built Mar 13 2019 11:20:51)
Using USB cable: FleaFPGA v2.5
1: STATE IDLE;
2: STATE RESET;
3: STATE IDLE;
4: SIR 8 TDI (E0);
5: SDR 32 TDI (00000000)
6: TDO (41111043)
7: MASK (FFFFFFFF);
Found unknown (00000000) device, but the bitstream is for LFE5U-25E.
Failed.
We need to add new board to supported boards
CRC retry is fixed but still binary upload will sometimes fail.
Manifests at first with CRC error, block sending is retried, CRC is OK
but uploaded code doesn't work.
ujprog is patched to use -D option to insert a pause after sending binary
block, before issuing 0x81 command to read checksum
It is not clear is it f32c bootloader problem or some usbserial or kernel serial issue
So when binary uploads fail, try to slow it down a bit:
ujprog -D100
From J.B. Langston
Side note, on Windows 10, uploading fails because ftd2xx.dll is missing and ujprog.exe won't run without it. I was able to fix this by downloading the FTDI driver from http://www.ftdichip.com/Drivers/D2XX.htm and putting the DLL in C:\Users\AppData\Local\Arduino15\packages\FPGArduino\tools\ujprog\1.0.0. I had to find ujprog.exe and run it manually to see the error dialog about the missing DLL. The Arduino IDE did not display any errors to indicate that this was the problem so this should probably be documented.
I encountered a bunch of warnings that usleep
is deprecated, and more importantly a critical error that 'EOPNOTSUPP' undeclared when compiling ujprog
in MinGW32 for Windows:
cp Makefile.win Makefile
make
Output:
gcc.exe -c ujprog.c -o ujprog.o -I.
[... snip ...]
c:\mingw\include\unistd.h:100:29: note: declared here
int __cdecl __MINGW_NOTHROW usleep( useconds_t )__MINGW_ATTRIB_DEPRECATED;
^~~~~~
ujprog.c: In function 'shutdown_usb':
ujprog.c:621:2: warning: 'usleep' is deprecated [-Wdeprecated-declarations]
ms_sleep(10);
^~~~~~~~
In file included from ujprog.c:55:
c:\mingw\include\unistd.h:100:29: note: declared here
int __cdecl __MINGW_NOTHROW usleep( useconds_t )__MINGW_ATTRIB_DEPRECATED;
^~~~~~
ujprog.c: In function 'exec_svf_tokenized':
ujprog.c:1488:9: error: 'EOPNOTSUPP' undeclared (first use in this function); did you mean 'WSAEOPNOTSUPP'?
res = EOPNOTSUPP;
^~~~~~~~~~
WSAEOPNOTSUPP
ujprog.c:1488:9: note: each undeclared identifier is reported only once for each function it appears in
ujprog.c: In function 'async_read_block':
ujprog.c:2788:4: warning: 'usleep' is deprecated [-Wdeprecated-declarations]
ms_sleep(backoff * 4);
^~~~~~~~
In file included from ujprog.c:55:
[... snip ...]
gcc.exe ujprog.o -lftd2xx -o "ujprog.exe" -s -static -L. -lftd2xx
The solution that worked for me here for the error: 'EOPNOTSUPP' undeclared
was the same as nmap/nmap#183 in adding these two lines to ujprog.c
:
#undef EOPNOTSUPP
#define EOPNOTSUPP WSAEOPNOTSUPP /* Operation not supported */
After that change, I was able to create an exe for ujprog
.
-a *.bit
; FAILS to find any files:C:\workspace-git\f32c_tools\ujprog>ujprog -P COM9 -a *.bit
ULX2S / ULX3S JTAG programmer v 3.0.92 (built Feb 13 2019 12:27:20)
*.bit: cannot open
-a
[explicit file name]; finds file, completes, FAILS to actually upload file:C:\workspace-git\f32c_tools\ujprog>ujprog -P COM9 -a ulx3s.bit
ULX2S / ULX3S JTAG programmer v 3.0.92 (built Feb 13 2019 12:27:20)
Sending ulx3s.bit: done.
C:\workspace-git\f32c_tools\ujprog>ujprog *.bit
ULX2S / ULX3S JTAG programmer v 3.0.92 (built Feb 13 2019 12:27:20)
Using USB cable: ULX3S FPGA 12K v3.0.3
open(*.bit) failed
Programming: 0% -
Failed.
C:\workspace-git\f32c_tools\ujprog>ujprog ulx3s.bit
ULX2S / ULX3S JTAG programmer v 3.0.92 (built Feb 13 2019 12:27:20)
Using USB cable: ULX3S FPGA 12K v3.0.3
Programming: 100%
Completed in 18.66 seconds.
Latest ujprog binary transfer changes
somehow broke ulx2s 3Mbit transfer over ftdi
manefest on linux (don't know for other platforms)
workaround is to use 115200 serial transfer
(select some other board with sram like scarab
or altera de0 nano) and upload to ulx2s
Use shorter flash erase block.
Instead of erasing flash in chunks of 64 KB blocks with SPI opcode 0xd8
erase in chunks of 4 KB block with legacy SPI opcode 0x20.
Should also improve compatibility among various flash chips.
Valentin from FLEAsystems http://www.fleasystems.com/fleaFPGA.html
succesfully ported f32c on his board with maximum stable core clock frequency of
55MHz and he's having issues with sio break detection timeouts.
this is how he fixed it in sio.vhd
Thanks to modifying the following line in sio.vhd, I am also now able to perform one-click upload from the Arduino IDE - very cool!! :-D
constant C_break_detect_incr: integer := 1 + 33 / C_clk_freq; -- For 81.25MHz use: "1 + 50 / C_clk_freq;"
We should check timeouts in sio and ujprog and how they are calculated,
to make them work more reliably on boundary cases
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