fahadmuslim Goto Github PK

avatar

Official code of our work, AVATAR: A Parallel Corpus for Java-Python Program Translation.

bitonic-sorting

Implementation of BitonicSorting algorithm on FPGA through SDAccel using Opencl as source code

blackeuro_vivadoskd_design

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-book

Digital Design with Chisel

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

chisel-examples

Chisel examples and code snippets

chisel-lab

Lab exercises for Chisel in the digital electronics 2 course at DTU

chisel3

Chisel 3: A Modern Hardware Design Language

chisel_labs_giki

These labs are based on Prof. Martin Shoeberl labs and intended as basic sessions to get one started with using Chisel with Nexys4 DDR FPGA board.

codegen

CodeGen is an open-source model for program synthesis. Trained on TPU-v4. Competitive with OpenAI Codex.

datalib

JavaScript data utility library.

dc_training

ece5745-tut3-pymtl

ECE 5745 Tutorial 3: PyMTL3 Hardware Modeling Framework

ece5745-tut5-asic-tools

ECE 5745 Tutorial 5: Synopsys/Cadence ASIC Tools

educational-materials

Educational materials for RISC-V

f-mac

https://caravel-user-project.readthedocs.io

freedom

Source files for SiFive's Freedom platforms

freepdk-45nm

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

fyp--risc-v-32-bit-matrix-mac

A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations

gemmini

Berkeley's Spatial Array Generator

giki_workshop_chisel_tayyab

high-level-synthesis-flow-on-zynq-using-vitis-hls

This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.

hls4ml-tutorial

Tutorial notebooks for hls4ml

intro-spacy-nlp

An introduction to using spaCy for NLP and machine learning

kc705

knn

low-power-asic-designs-based-on-cpf

This repository contains part of our work done to infer power intent at a higher level of abstraction i.e. at the system-level. The designs span from simpler basic computing blocks to more practical HW acclerators.

mesh-transformer-jax

Model parallel transformers in JAX and Haiku

neural-language-model

A tutorial on how to build your own Neural Language Model