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neural-language-model

A tutorial on how to build your own Neural Language Model

nexys4ddr_sevensegment

This repository is based on the labs developed by Prof. Martin Shoeberl and uses Chisel for digital design. I have added the seven segment decoder and a hex up counter that prints the values on the seven segment display of a nexys4 ddr board.

openlane

This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

opensta

OpenSTA engine

pytorch-beginner

pytorch tutorial for beginners

riscv_pipeline_core_merl

This repository contains the design files of RISC-V Pipeline Core

riscv_single_cycle_core

This repository contains the design files of RISC-V Single Cycle Core

riscv_single_cycle_core_merl

This repository contains the design files of RISC-V Single Cycle Core

rocket-chip

Rocket Chip Generator

rvalp

RISC-V Assembly Language Programming

single-cycle-risc-v-in-verilog

This repository contains the verilog code files of Single Cycle RISC-V architecture

sky130_blender_renders_tutorial

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

skywaterlib-synopsysdb

skywater_synopsysdb

This repository contains the various steps that shall enable one to convert the skywater 130nm library to the db format to be used in Synopsys design compiler.

sphinx_materialdesign_theme

Material Design Html Theme for Sphinx.

springschool-supercomputing-and-parallel-programming

Supercomputing and Parallel Programming Spring School

tapeout_pakistan_training

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

uetrv-pcore

Linux Capable 32-bit RISC-V based SoC

vitis-hls-introductory-examples

vitis-tutorials

Vitis In-Depth Tutorials

vitis_accel_examples

Vitis_Accel_Examples

vitis_embedded_platform_source

vitis_hero

xup_high_level_synthesis_design_flow

AMD Xilinx University Program HLS tutorial