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FPGA implementation of pose detection with Kalman filter. (verilog)

License: GNU General Public License v3.0

C++ 0.01% Python 0.01% Verilog 34.17% HTML 0.16% Common Lisp 0.01% TeX 0.02% VHDL 65.13% Tcl 0.02% C 0.06% Pascal 0.01% V 0.35% Stata 0.01% Shell 0.06% Forth 0.01% JavaScript 0.01% Batchfile 0.01% PureBasic 0.01%

pose-detection-of-mpu6050-based-on-fpga's Introduction

Pose Detection of MPU6050 Based on FPGA

文件夹说明

algorithm

卡尔曼滤波的C/CPP版本

docs

说明文档

ip

使用到的部分ip

project

完整的工程文件

vivado版本:2021.02 ML版

rtl

rtl代码

tb

rtl的testbench代码

wave

部分信号的时序图(还没整理好)

debug

debug过程中用到的脚本和记录的数据,其中data_gen.py是用来生成tb测试数据的,checksum_test.py是用来验证匿名上位机协议checksum的,data_process.py是用于uart数据帧对齐的。

使用说明

打开工程后的top层次结构如下:

image-20220330102755103

image-20220330103458950

其中keyboard和dynamic_digital是自己写的ip,分别用于键盘输入,数码管动态显示,工程里也包括了。

本项目仅计算了ROLL和PITCH两个角度,没有计算YAW角,YAW默认为0。

整体架构说明

基于FPGA的MPU6050姿态解算(1) | DOA's Blog (floral.github.io)

top信号说明

input				clk_in,		//50m clk in
input				rst_n,

input	[3:0]		col_in,		// 4x4键盘矩阵的列输入

output	[3:0]		row_out,	// 4x4键盘矩阵的行输出

output				scl,		// i2c scl
inout				sda,		// i2c sda

input				rx,			// uart rx, 本工程没用,不连也行
output				tx,			// uart tx

output	[7:0]		seg_out,	// 单个数码管段码输出
output	[5:0]		dig_out		// 不同数码管有效/使能输出

I2C IP修改说明

在原版的IP基础上,增加了i2c_data_numi2c_ack[6]信号,前者表示I2C连续写入/读取的数据量(以字节为单位),后者标志主机发送STOP完成。使用的时候只需在给i2c_config赋值的同时给i2c_data_num赋值即可。

完成指定数据量的写入/读取之后,i2c_ack[6]信号会被拉高。

Kalman Ctrl

该模块是一个有四个状态的状态机:WAITCONFIGCALIBRATECALCULATE

控制整个流程的不同状态切换。

CALIBRATE状态下,I2C是连续读取的,即I2C_Config不切换;在CALCULATE状态下,I2C的读取频率是由mpu_read_timer决定的,默认频率是800Hz(是由UART 115200速率经过计算后的最合适频率),每出现一次timer_tickI2C_Config才切换为I2C_Continuous_Read_Byte状态,i2c_ack_6_pos_in被拉高后则进入WAIT状态。

data packing

本项目使用的上位机是<匿名上位机>,所以协议使用的也是该上位机的协议。

上位机下载地址: 匿名科创] (anotc.com)

匿名上位机(V7)基于串口的简单使用_Silent Knight的博客-CSDN博客_匿名上位机v7

cordic_arcsin_arccos

注意该模块中有一个需要读入的atan数据文件atan.dataproject/vivado/Pose_Detection_With_Kalman_Filter/C_model/下。

UART with fifo

uart速率默认为115200

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