The gm-study-e1 from fm4dd

gm-study-e1's Introduction

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I enjoy designing and building electronics hardware (development boards), and learning how to code low-level. I have been working on FPGA PMOD design, on solar position tracking for photovoltaic systems, and with a long work history in Information Security some repos are security-related.

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gm-study-e1's Issues

Evaluation board E1 IO bank NA intermittent pin contacts B1, B2

The app boards get intermittent pin contact for pins IO_NA_B1 and IO_NA_B2. The boards have been checked to be OK, and the issue occurs across different app boards and board types. The signal measurements on the E1 NA bank connector surface-mount solder joints confirm a good signal. The suspected root cause is at the evaluation board E1 bank connector for Bank NA.

The affected signals on NA_B1 and NA_2 connect to 7-Segment module HEX2, LED segments DP and A.

I would need a second E1 board to fully confirm it. My board may have a faulty NA connector. The E1 evaluation boards BCP thickness of 1.2 mm is rather weak, which lends to bending.

Brighten up the 7-segment LED modules

The resistor bank RA values for the HDSP-7501 7-segment LED modules are too strong at 200 Ohm. They should be reduced to 180/160 Ohm.

Buzzer bz1 low sound volume

The volume of buzzer bz1 is rather low. This could improve by raising the GPIO signal voltage. There is still one free signal path A1/B1 on U2...

5V signal level conversion failure on connector J1

Per Texas Instruments application note SLV675B, the signal lines operated by the TI LSF204 level translation circuits (U2,U3,U4) need pull-up resistors. They need to be added in for high side (B-side), the low-side (A-side) is recommended for signal integrity. Need to verify and test the signal levels on J1 in detail. 5V power is present.

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