fpga-mafia / fpga_mafia Goto Github PK

• What are the IPs you are going to design
• what role they have in the system,
• architecture, microarchitecture, simulation, verification
• FPGA
• Integration to the MEGA_PROJECT

Break the tasks into milestones (according to dependency)

Design a simple "xor" module + tracker
source/cache
verif/cache/tb
modelsim/cache
target/cache

Add a directory called "cache" under the "source" directory.
In the directory add a file called "README.md"
In the file, please write a short description of the project you are starting as you understand it. (1-3 paragraphs)

Close this issue using a commit with the comment "close #<issue_number>"

DO be able to commit, you may need to make a small change.
Recommend changing one of the READMEs.

Using the "host" (personal computer) python terminal allows communication with the "device".
Load programs & data to the FPGA using the UART

router - create the router folders placeholders

align all the trackers to Q102

Please add the correct directories & READMs in the following hierarchies:

• source/cache
• verif/cache
• -- tb
• -- tests
• modelsim/cache
• target/cache

big_core - support RGB mode VGA SW

Big_core - move the tracker logic to its own file, then use include in the tb
See reference in cache

welcome to use reference:

module round_robin
import utils_pkg::*;
(
    input   logic                         clk,
    input   logic                         rst,
    input   logic                         enable,
    input   logic [NUM_TQ_ENTRY-1:0]      candidates,
    output  logic [NUM_TQ_ENTRY_LOG2-1:0] enc_winner

);
logic [NUM_TQ_ENTRY-1:0] cur_winner;
logic [NUM_TQ_ENTRY-1:0] last_winner;
logic [NUM_TQ_ENTRY-1:0]      mask_out;
logic [NUM_TQ_ENTRY-1:0]      mask_candidate;
logic [NUM_TQ_ENTRY-1:0]      first_top;
logic [NUM_TQ_ENTRY-1:0]      first_bottom;
logic hit_top;
`LU_RST_EN_DFF(last_winner , cur_winner , clk, enable, rst)

always_comb begin
        mask_out = '0;
    for(int i =0; i < NUM_TQ_ENTRY; i++ )begin
        mask_out[i] = (last_winner > i);
    end
end
assign mask_candidate = (candidates & (~mask_out));
`FIND_FIRST(first_top    , mask_candidate)
`FIND_FIRST(first_bottom , candidates)

assign hit_top = (|first_top);
assign cur_winner = hit_top ? first_top : first_bottom;
`ENCODER(enc_winner, cur_winner)

//====================
// winner[1:0]       = 2'b10  ;
// mask_out[3:0]     = 4'b0011;
// candidate[3:0]    = 4'b1101;
// first_top[3:0]    = 4'b0100;
// first_bottom[3:0] = 4'b0001;
endmodule

Create something similar to the RVC_ASAP memory wrap

Make sure to solve the 32 bit alien access withing the mem_wrap and NOT in the big_core module
Create a ditectaed test to check all the memory access lw, lh, lb, lhu,,lbu, sw,sh,sb

• @danielk532
• @yeonatanPerelman & @ShmuelSfez

You may use the current implementation we designed together.

I would like to be able to read your README for each model and execute your "local" core.
Eventually, you will modify the core to be the one we need. (3/7 stage Pipeline)

Please mark yourself as done once you pushed a solution to a branch
Once you are all done, you may close the issue as completed

• @danielk532
• @yeonatanPerelman
• @ShmuelSfez

big_core - support Key board interface in SW

https://www.youtube.com/watch?v=7aXbh9VUB3U

• Please add lots and lots of comments!
• keep assigning the logic backward to what generated it.

@danielk532
Add a directory called big_core.
In the directory add a file called "README.md"
In the file, please write a short description of the project you are starting as you understand it. (1-3 paragraphs)

Scaledown resolution and support RGB.

Explain the cases of WR after Wr to the same CL
Explain Rd After WR to same CACHE line with word miss (HIT MB + MISS WORD)
Explain Rd After WR to same CACHE line with word HIT ( HIT MB + HIT WORD)(response from MB and not the Pipe)

How the fill is used for both WR miss fill & Read

How the RD miss will stall the Core.
How the MB merges the Writes & the Fills

How the FIll with a "rd_indication" will go through the pipe to answer and send the rd response in q3.

How do we never allocate a new entry for the request to the same CL.

• In case of hit in "FILL_LU" the RD/WR request will 100% hit the Cache, no need to allocate a new TQ entry

The MB is a structure that works per TQ entry.

The Documentation:

HAS_RVC_ASAP.pdf

Please mark your name done once you are done reviewing the RVC_ASAP.

I may have read this already, but it's a good idea to reread it - mainly the part that you did not understand.

• @danielk532
• @noamsabb
• @yeonatanPerelman
• @ShmuelSfez

• Daniel, Shmuel, Yonatan Open Git hub account
• Amichai - will need to add you to the repository as contributors

Please mark this as done once you are all able to access this reposetory

1. add the description of the transaction as a header and not in line.
2. add a tracker to both the pipe input & the pipe output. (q1 & q3)
3. change the name the top level tracker to something more representative (cache_top_trk.log)
4. add to the top level tracker the FM fill.
5. support pipe tracker "Fill" opcodes

Close this issue using a commit with the comment "close #<issue_number>"

DO be able to commit, you may need to make a small change.
Recommend changing one of the READMEs.

peek
poke
fwrite/printf
scanf
draw line
draw

big_core - support Key bord interface in HW

Example:
When running python build.py -test alive -debug -full_run -proj_name big_core
I expect that if we had an HW compilation error, the build wouldn't continue to the simulation stage.

big_core - fix build + TB to create a target/big_core/test_reults/<test_name>

This directory will contain the tracker's output per test.
(Currently, the tracker output override each other)

1. create a simple description of the fifo_arbiter IO
2. desgin the module
3. use the FIFO you created and have 3 institutions in the fifo_arbiter
4. using the round-robin, arbitrate the FIFO.
5. Don't forget to have the "full" indication to back preasue

Instructions for running the build.py
adding it as a discussion

Has 3 flags:

• -app | compile the RISCV SW into SV executables
• -hw | compile the RISCV HW into simulation
• -sim | start simulation
  • Choose which test to run - plus+args to point to the correct 'memory' that was generated

Make sure the trk.log files get the unique directory of the specific test

1. Add a struct that is called cache_pipe_struct add the fields:
   For now, lets not optimize anything - just add any information on the transaction life-cycle into the pipe struct

• lu_valid,
• lu_set,
• lu_tag,
• hit,
• miss,
• mb_hit_cancel
• set_ways_mru[3:0],
• set_ways_valid[3:0],
• set_ways_victim[3:0]
• set_ways_hit[3:0],
• set_ways_enc_hit[2:0],
• fill_cl_data[127:0]
• fill_valid
• lu_opcode[1:0] // RD_LU, WR_LU, FILL_LU

Each cycle has the sampled version and the updated version ( cache_pipe_lu_q2 ,pre_cache_pipe_lu_q2)

//====================
//    Pipe stage 1
//====================
always_comb begin
  cache_pipe_lu_q1 ='0; //this is the default value
  cache_pipe_lu_q1.valid         = ...q1 ;
  cache_pipe_lu_q1.opcode    = ...q1 ;
  cache_pipe_lu_q1.set            =  ...q1 ;
  cache_pipe_lu_q1.tag           =  ...q1 ;
  cache_pipe_lu_q1.fill_data     =  ...q1 ;
end //always_comb


//====================
//    Pipe stage 2
//====================
`DFF(pre_cache_pipe_lu_q2, cache_pipe_lu_q1, clk)
always_comb begin
  cache_pipe_lu_q2                         =pre_cache_pipe_lu_q2; //this is the default value
  cache_pipe_lu_q2.set_ways_valid = ...;
  cache_pipe_lu_q2.set_ways_tags = ...;
  cache_pipe_lu_q2.set_ways_mru  = ...;
  cache_pipe_lu_q2.set_ways_hit    = ...;
  cache_pipe_lu_q2.hit                    = ...;
  cache_pipe_lu_q2.miss                = ...;
  cache_pipe_lu_q2.data_array_address   = {pre_cache_pipe_lu_q2.set , pre_cache_pipe_lu_q2.set_ways_enc_hit};

end //always_comb

//====================
//    Pipe stage 3
//====================
`DFF(pre_cache_pipe_lu_q3, cache_pipe_lu_q2, clk)
always_comb begin
  cache_pipe_lu_q3                        =pre_cache_pipe_lu_q; //this is the default value
  .. 
end

Use the struct to replace the current logic in the cache_pipe.

logic [NUM_WAYS-1:0] way_tag_match_q2;
logic [WAY_WIDTH-1:0] way_tag_enc_match_q2;
logic                 valid_match;
logic [WAY_WIDTH-1:0] way_tag_enc_match_q3;

Go over Cache HAS - FIx the comments, Add your own content & Notes:

Make sure you add time, pc, opcode, address, and data.
The data in read is the load data, and the data in write is the store data.

Please mark yourself as done once you pushed a solution to a branch
Once you are all done, you may close the issue as complete

• @danielk532
• @yeonatanPerelman
• @ShmuelSfez

1. use the macros
2. Don't use an async reset
3. Use mean-terms
4. don't use reg/wire - only logic
5. interface - make sure to declare the type explicitly
6. remove all <TABS> from design!!!!!
7. Use the Push/Pop terminology on the interface
8. indentation!
9. Explicit signal width. ('0 is also acceptable)

step 1:
Create the i_mem + d_mem as you see here:
https://github.com/amichai-bd/riscv-multi-core-lotr/tree/master/source/gpc_4t/rtl

Add a new module called "mem_wrap" which holds 2 modules:

• inst_mem
  • fabric : read/write
  • Core : read
• data_mem
  • fabric : read/write
  • Core : read/write

Please make the standard interface to match the FPGA style - see reference here:
https://github.com/amichai-bd/riscv-multi-core-lotr/blob/master/source/gpc_4t/rtl/d_mem_wrap.sv

Please note: the FPGA std memory is only 32-bit aligned!
You must ensure any non-32-bit aligned request will read/write correctly!
This is done by shifting the data & enable it correctly!

Please review the CACHE HAS.
https://1drv.ms/u/s!Apu_j5InzXdpgdB5rEItxXRam84YPQ?e=FQYR2w

Ask any questions on the document (using the comment option in the word) and start working on fixing up the document.

Each one needs to make there own branch, make a change (or add new files)
then push to origin & send a pull request

Not functinal yet - just skelaten for future.
Please add lots of comments:
See reference:

1. tag array - use the correct parameter
2. data array - use the correct parameter

big_core - move the c program to verif/big_core/test/<test_name>.c

Has 3 flags:

-app | compile the RISCV SW into SV executables
-hw | compile the RISCV HW into simulation
-sim | start simulation

Choose which test to run - plus+args to point to the correct 'memory' that was generated. - Leave this for last.
Make sure the trk.log files get the unique directory of the specific test

Use references from other HAS.

The most important is define interface & interface constraints.

Make sure to use word correctly!

BIU:
https://us02web.zoom.us/rec/play/AgNFYK1pAD007BcN7a4FbJYP-ywdCFJPdibAVJxmCOuQWP64T1jJp24JcdlD24jlTnTo4bONbyqgHbzP.-XeGhQejBA586qWm?continueMode=true&_x_zm_rtaid=df0I1OSLQYqhfvDYLuPKWg.1666080351879.0e61c041d874a0bb0cad8a39967ddc47&_x_zm_rhtaid=18

Techinion:
https://technion.zoom.us/rec/share/SKocYROkZP3Yz4OApGyAbb343mj8cjjD174V4C5hsLvBIt4NpPsYtCajKdDl12hk.4Z6ekW9gF3u048ml?startTime=1666073026000
Use this password to connect:

2+.RqPC+

Please mark your name done once you watch both presentations:

• @danielk532
• @noamsabb
• @yeonatanPerelman
• @ShmuelSfez

The last one to mark his name, please colse this issue with a comment.

Please see the link:
https://1drv.ms/u/s!Apu_j5InzXdpgdB5rEItxXRam84YPQ?e=gS34p0

You have a template and reference to start the Big core HAS

Switch
LED
7SEG
Button

@yeonatanPerelman & @ShmuelSfez
Add a directory called "mesh" under the "source" directory.
In the directory add a file called "README.md"
In the file, please write a short description of the project you are starting as you understand it. (1-3 paragraphs)

Close this issue using a commit with the comment "close #<issue_number>"

DO be able to commit, you may need to make a small change.
Recommend changing one of the READMEs.