Related Issues (20)
- Add `-dut` flag to `sanity_check.py` file to run sanity test on local machine with specific core
- Add `PS2_fibbonacci.c` test to `rv32i_level0_cfg_intrpt_no_ref` file HOT 4
- Automate regression analysis and have it as artifacts in the PR to main
- Refactor the D_Cache TB verification and design
- Cache - support partiol read/write (byte enable)
- WRite the WW12 weekly HOT 1
- update the letters font
- Using the FPGA of-die memory, sdram | Create a POC HOT 2
- Add the VGA CounterX CounterY to the CR space so its accessible from timing HOT 1
- writing MC (memory controller) for communication between host and SDRAM HOT 1
- Refactor the CR structure in the core_rrv
- Rename core_rrv to big_core
- `core_rrv` has been renamed to `big_core` - ONLY READ ISSUE HOT 4
- Noam - Write a combined weekly for WW14-15-16
- Jacob - Write a combined weekly for WW14-15-16
- Design `mem_ss` to work with SDRAM controller and D_CACHE
- add M extension to big_core
- Write weekly for WW 19-20-21-22 HOT 1
- Organize the mem_ss source directory. HOT 2
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from fpga_mafia.