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Distributed Accelerator OS
Hi
I used latest project and successfully generated bit file for vcu118, but after loading the bit, I saw LED[1] and LED[2] ON, while LED[3] & LED[4] & LED[5] are blinking.
According to the top rtl
It seems pcie is not linked up (LED[0] OFF), while rx_aligned_led is low (LED[6] OFF).
Based on my configuration, I only used 10G network, so rx_aligned_led can be negelected.
I didn't change anything in the source code, and the pcie connector was good too. Any clues why it didn't link up?
Thanks!
Hi,
Is there any example of using davos with qdma + dpdk? if not, would that be hard to port xdma to qdma + dpdk? what would be the potential challenges?
Best,
Yang
Could you please provide the test methods?
Hi, i'm following the project. I have managed generate the bitstream, but i have no idea on how to test it. In previous version of readme, it show some ways to test the project. Such as "ping 10.1.212.209" and "echo 'hello world' | netcat -q 1 10.1.212.209 7", which i have already succeed.
Can you tell me the test method of the davos project?
Thanks !
Hi
Great project about fpag! Just wonder if you could share the source project file for setting up mig_axi_mm_dual.dcp, such as I can migrate it to Netfpga-SUME (XC7VX690T-FFG1761-3)?
Best,
Yang
This project seems to have no channel which TOE's application layer interface communicates with the host through XDMA transmission
TOE's application layer interface(confige and data) How to reach the host?
Hi I have some questions about current davos project and the original 'fpga-network-statck' project:
Thanks in advance!
As far as I can tell, the traversal kernel (getValueForKeyAt(...)), the consistency kernel (getConsistent(...)) and the shuffling kernel (setPartitionerMapping(...)), which you describe in your paper "StRoM: smart remote memory", are missing. Is there any way to get access to the corresponding code?
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