[Verilog][Code generation] Input not connected to a wire in the Verilog code generation about icestudio HOT 5 CLOSED

// Code generated by Icestudio 0.3.0-beta3-dev
// Wed, 08 Feb 2017 19:35:02 GMT

`default_nettype none

module main (
 input vd5501f,
 output v834948,
 output [0:6] vinit
);
 wire w0;
 wire w1;
 wire w2;
 assign w0 = vd5501f;
 assign v834948 = w1;
 main_v9ef512 v9ef512 (
  .clk(w0),
  .q(w1),
  .q_n(w2)
 );
 assign vinit = 7'b0000000;
endmodule

module main_v9ef512 (
 input d,
 input clk,
 output q,
 output q_n
);
 reg qi = 0;
 always @(posedge clk)
   qi <= d;
 assign q = qi;
 assign q_n = ~qi;
endmodule