Comments (3)
Strange as it seems, that is the synthesizer's way of stating this:
"You did not put an else
at the end of every if
statement, even one simple if
statement, or an if
statement followed by any chain of else if
statements, to close off the input space of possibilities"
AND
"You did not put a default
at the end of every case
statement, thus ensuring it has full coverage of its input values"
Here's a quick description that you can find better documented elsewhere:
Hardware generated by Verilog is very open-ended, but you have to follow some simple rules like that to keep it under control. For these conditions (branches), if all the possible data values are not "covered" to describe & derive your outputs, then it believes you are leaving an input value as it was till next transition. To do that, the synthesizer creates a latch. Why is it telling you you didn't want the latch? I'm not quite sure, but consider yourself lucky that it stopped you...?
I think everyone can agree the error messages are awful, sometimes. Not much guidance...
But for Icestudio to add a validation layer to check your if
s and case
s before it sends the code down to Yosys... I'm guessing that might be taking on too much responsibility from Yosys, and opening up a can of worms.
from icestudio.
Similarly, thinking of improving the validations and errors:
Why doesn't the iverilog
layer that does the "Verify" (Ctrl R) do a simple check like that and complain about incomplete if
s and case
s? It must be because of the open-ended, very flexible interpretation of the HDL. But does iverilog
have some switch that would do a more strict check? That would make sense...
Would be brought to your attention early, long before sending to Yosys
from icestudio.
from icestudio.
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