TTA-based Co-Design Environment (TCE) is an open application-specific instruction-set processor (ASIP) toolset for design and programming of customized co-processors (typically programmable accelerators). It is based on the energy efficient Transport Triggered Architecture (TTA) processor template.

The toolset provides a complete retargetable co-design flow from high-level language programs down to FPGA/ASIC synthesizable processor RTL (VHDL and Verilog generation supported) and parallel program binaries.

Processor customization points include the register files, function units, supported operations, and the interconnection network.

TCE has been developed by several researchers (and research assistants) of Tampere University (Finland) and various other international contributors since the early 2003.

Links:

• The toolset web pages
• Customized Parallel Computing group's home page. CPC leads the development of TCE.