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Perhaps, it is worth giving more emphasis to DSLs in our memo. The following DSLs and transformations between them could be discussed:

• Signal Transition Graphs (STGs) -- a low-level (signal-level) DSL for specifying resilient asynchronous controllers. Supported by Workcraft.
• Conditional Partial Order Graphs (CPOGs) -- an intermediate-level (microarchitecture-level) DSL for specifying processor instructions as collections of partial orders. Supported by Workcraft.
• Dataflow Structures (DFSs) -- an intermediate-level (dataflow graphs) DSL for specifying reconfigurable dataflow graphs. Supported by Workcraft.
• Event-B -- a high-level DSL for formal specification of system requirements and system reconfiguration. Supported by Rodin toolset.
• Verilog -- a low-level DSL for hardware description, supported by standard industrial design flow. Workcraft can generate Verilog from models such as STGs/CPOGs.
• Farfalle -- an intermediate-level (microarchitecture-level) Embedded DSL, that we propose to use as a bridge between Event-B and STGs/CPOGs/DFSs. Here is where we can benefit greatly from Haskell's powerful type system, and here is where we plan to achieve fast prototyping.

One could think of connecting the above DSLs into the following pipeline:

Event-B <=> Farfalle => (STGs + CPOGs + DFSs) => Verilog