mc-asm's Introduction

mc-asm

mc-asm provides a Python API for turning assembly into machine code, providing rich symbolic information.

Copyright and Acknowledgments

This code is licensed under the MIT license. See the LICENSE file in the project root for license terms.

This project is sponsored by the Office of Naval Research, One Liberty Center, 875 N. Randolph Street, Arlington, VA 22203 under contract # N68335-17-C-0700. The content of the information does not necessarily reflect the position or policy of the Government and no official endorsement should be inferred.

The header files under the src/llvm-headers/ directory are copied from the LLVM project and are licensed under the Apache License v2.0 with LLVM Exceptions (a copy of that license is included in the src/llvm-headers/ directory).

The following files from the open-source LLVM project are included in the MCASM repository.

Files:
- AArch64MCExpr.h (from llvm/lib/Target/AArch64/MCTargetDesc/)
- MipsMCExpr.h (from llvm/lib/Target/Mips/MCTargetDesc/)
Project Name: LLVM
Project Version: 14.0.6
License: Apache License v2.0 with LLVM Exceptions

mc-asm's People

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mc-asm's Issues

Should fix a bug, jump address or call address

In the default execution of

asm(
R"(
mov %eax, %eax
call 0x12345678
)"
);

[
  {
    "kind": "changeSection",
    "section": {
      "alignment": 1,
      "characteristics": 1610612768,
      "class": "MCSectionCOFF",
      "isVirtual": false,
      "kind": {
        "isBSS": false,
        "isCommon": false,
        "isData": false,
        "isExecuteOnly": false,
        "isGlobalWriteableData": false,
        "isMergeableCString": false,
        "isMergeableConst": false,
        "isMetadata": false,
        "isReadOnly": false,
        "isReadOnlyWithRel": false,
        "isText": true,
        "isThreadBSS": false,
        "isThreadLocal": false,
        "isWriteable": false
      },
      "name": ".text"
    }
  },
  {
    "data": "89c0",
    "fixups": [],
    "inst": {
      "desc": {
        "canFoldAsLoad": false,
        "hasDelaySlot": false,
        "hasOptionalDef": false,
        "hasUnmodeledSideEffects": false,
        "implicitDefs": [],
        "implicitUses": [],
        "isAdd": false,
        "isAuthenticated": false,
        "isBarrier": false,
        "isBitcast": false,
        "isBranch": false,
        "isCall": false,
        "isCompare": false,
        "isConditionalBranch": false,
        "isConvergent": false,
        "isExtractSubregLike": false,
        "isIndirectBranch": false,
        "isInsertSubregLike": false,
        "isMoveImmediate": false,
        "isMoveReg": true,
        "isNotDuplicable": false,
        "isPredicable": false,
        "isPseudo": false,
        "isRegSequenceLike": false,
        "isReturn": false,
        "isSelect": false,
        "isTerminator": false,
        "isTrap": false,
        "isUnconditionalBranch": false,
        "isVariadic": false,
        "mayLoad": false,
        "mayRaiseFPException": false,
        "mayStore": false,
        "numDefs": 1,
        "variadicOpsAreDefs": false
      },
      "flags": 0,
      "opcode": "MOV32rr",
      "operands": [
        {
          "kind": "reg",
          "reg": "EAX"
        },
        {
          "kind": "reg",
          "reg": "EAX"
        }
      ]
    },
    "kind": "instruction"
  },
  {
    "data": "e800000000",
    "fixups": [
      {
        "flags": [
          "IsPCRel"
        ],
        "name": "FK_PCRel_4",
        "offset": 1,
        "targetOffset": 0,
        "targetSize": 32,
        "value": {
          "kind": "binaryExpr",
          "lhs": {
            "kind": "constant",
            "useHexFormat": false,
            "value": 305419896
          },
          "opcode": "Add",
          "rhs": {
            "kind": "constant",
            "useHexFormat": false,
            "value": -4
          }
        }
      }
    ],
    "inst": {
      "desc": {
        "canFoldAsLoad": false,
        "hasDelaySlot": false,
        "hasOptionalDef": false,
        "hasUnmodeledSideEffects": false,
        "implicitDefs": [],
        "implicitUses": [
          "ESP",
          "SSP"
        ],
        "isAdd": false,
        "isAuthenticated": false,
        "isBarrier": false,
        "isBitcast": false,
        "isBranch": false,
        "isCall": true,
        "isCompare": false,
        "isConditionalBranch": false,
        "isConvergent": false,
        "isExtractSubregLike": false,
        "isIndirectBranch": false,
        "isInsertSubregLike": false,
        "isMoveImmediate": false,
        "isMoveReg": false,
        "isNotDuplicable": false,
        "isPredicable": false,
        "isPseudo": false,
        "isRegSequenceLike": false,
        "isReturn": false,
        "isSelect": false,
        "isTerminator": false,
        "isTrap": false,
        "isUnconditionalBranch": false,
        "isVariadic": false,
        "mayLoad": false,
        "mayRaiseFPException": false,
        "mayStore": false,
        "numDefs": 0,
        "variadicOpsAreDefs": false
      },
      "flags": 0,
      "opcode": "CALLpcrel32",
      "operands": [
        {
          "imm": 305419896,
          "kind": "imm"
        }
      ]
    },
    "kind": "instruction"
  }
]

The actual address of the generated assembly code is 0x00000000

The module address is missing here, so llvm does not calculate the address that should be called correctly.

Or maybe I don't use ATT or INTEL assembly syntax.

Please advise me

Thank you very much!

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grammatech / mc-asm Goto Github PK

mc-asm's Introduction

mc-asm

Copyright and Acknowledgments

mc-asm's People

Contributors

Stargazers

Watchers

Forkers

mc-asm's Issues

Should fix a bug, jump address or call address

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