How to run
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This Makefile is made to be used with Synopsys VCS but it should be easily adaptable to any SystemVerilog simulator.
To run the simulation you just need to type:
$ make -f Makefile.vcs
Configuration
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You'll need to edit the Makefile.vcs file and change the variable 'UVM_HOME' to your UVM installation.
Explanation of the code
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An explanation of this UVM testbench can be found at: http://colorlesscube.com/uvm-guide-for-beginners/