gzhx-a Goto Github PK

eecs119-circuit-design

Use Cadence Software on a Linux server to simulate logic design flow. Included basic gate structures (AND, OR, Not) using MOSFETS and also integration of gates to make full adders and circuits based on given requirements.

elasticpost

POST code for second order elastic constant

elevator-controller

数字逻辑作业-电梯控制器设计

elevator-simulator

电梯模拟系统，基于verilog，带LED屏幕显示驱动，可下至FPGA板中

elevatorcontroller

一个简易的8层电梯控制器，使用verilog HDL语言描述 / a simple elevator controller works with verilog HDL

fir_low_pass_filter

16bit输入信号的8阶FIR低通滤波器

fir_lowpass_filter

fpga

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga_homework

自动电梯控制系统

road2filter

滤波器设计之路（The road to filter-design, including FIR, IIR, sinc, Butterworth, etc.）

ustb_verilog_elevator

北京科技大学 数字逻辑 电梯