hacklinux / mipscpu-1 Goto Github PK

Project : *MIPS RISC32*
Author  : *Alex Zhang ([email protected])*
Features:
1.RTL Status 
  * Jun.03.2014
    MIPS CPU testbench is already and basic rtl compile is OK. 
  * Jun.04.2014
    Clean up the vcs warnings like port width mismatch, and signal declaration. 
    Add the memory dumping in the test_cpu.v.
  * Jun.05.2014
    The case add.rom can be passed with adding NOP before add instruciton
  * Jun.06.2014
    Add the Data forwarding unit 
  * Jun.09.2014
    Add the Data hazard detection

2.Functions

3.Tests
  3.1 add.rom ; Figure 2.13
      load $s1, 100($s0) ; 8E110064
      load $s2, 104($s0) ; 8E120068
      add  $s3, $s1, $s2 ; 02329820
      add.drom ;load into ram. 
      @64 00000001
      @68 00000002