I'm using cli based verilog compiler to build my lab tasks/projects on mac. I'm Computer Engineering student and learning verilog under Digital System Design course in 7th semester.

This repository is to help macOS and linux users who have just started learning verilog, so that they don't go through to those problems that i have faced. I'm the only mac user in my class. Whole class is using Modelsim for verilog. So here I face the difficulty because Modelsim does not support mac. So following are the instructions that how i setup development environment, and also there are my lab tasks as example codes.

I'm using vscode as an editor tool and using leafvmaple.verilog which provides a nice interface(button) to run .v file, and ericsonj.verilogformat extension which automatically formats the code. Installation steps are written in their respective README.md files. Also, I'm using scansion.app for GUI simulation.

If you have iverilog and scansion.app then you can also generate output using following commands in terminal.app:

    $ iverilog -o <task1_tb.v.out> <task1_tb.v>
    $ vvp <task1_tb.v.out>
    $ open -a Scansion <task1.vcd>

The above commands I used to run lab2/task1_tb.v. You need to write test bench (ie: _tb.v) to test your code.

• https://iverilog.fandom.com/wiki/Installation_Guide
• https://www.swarthmore.edu/NatSci/mzucker1/e15_f2014/iverilog.html
• https://iverilog.fandom.com/wiki/Getting_Started

Pull requests are always welcome. Happy coding :D