SystemVerilog code for generating a Gray code of arbitrary width.

I needed an efficient, easy way to generate gray codes for dual clock FIFOs. It's a pain to manually write out a gray code. Why not let a module do the heavy lifting for you?

1. Take files from src/ and add them to your own project. If you use hdlmake, you can add this repository itself as a remote module.
2. Other helpful modules are also available in this GitHub organization.
3. Consult the testbench in test/gray_code_tb.sv for example usage.
4. Read through the parameter descriptions in gray_code.sv and tailor any instantiations to your situation.
5. Please create an issue if you run into a problem or have any questions.

• Balanced gray codes