MultiZone® Security TEE for Arm® Cortex®-M is the quick and safe way to add security and separation to any Cortex-M based device. MultiZone® software can retrofit existing designs. If you don’t have TrustZone®, or if you require finer granularity than one secure world, you can take advantage of high security separation without the need for hardware and software redesign, eliminating the complexity associated with managing a hybrid hardware/software security scheme.
Hi!
I am trying out the MultiZone Cortex M product on the RA6M3 renesas board, and I had a few questions regarding that.
I was trying to change the system clock speed by setting the ICLK to 1/8 (30 MHz) in the configuration.xml file in e2studio. However, even after I set it and change everything, the clock speed doesn't actually change. I was wondering if it was because of MultiZone. Is MultiZone setting a clock speed on its own? Are the developers not allowed to set their own clock speed?
I know that most low level Cortex M processors do not have an internal cache. However, this product is supposed to run even on processors such as the Cortex M33. Therefore, I wanted to ask if there is any precaution being taken to prevent cache side channel attacks? For example, is the cache cleared when a context switch happens between zones?
Hello,
Using the tick parameter in the multizone.cfg file, if I set the tick time to be 10 ms, does that mean that each zone is run for 10 ms completely before being interrupted, or is the context switch (or some other work) done within that 10 ms?
And is a zone interrupted in any way by the kernel before it completely executes for 10 ms?
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