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3.0 3.0 0.0 39.01 MB

Final project of NUS Embedded Hardware System Design module.

Home Page: https://wiki.nus.edu.sg/pages/viewpage.action?pageId=167809322

License: MIT License

Verilog 17.19% VHDL 36.13% Tcl 0.57% C++ 2.49% SystemVerilog 0.52% C 9.39% HTML 32.34% V 0.54% Pascal 0.01% Stata 0.04% Shell 0.06% Forth 0.01% JavaScript 0.03% Batchfile 0.01% SuperCollider 0.11% Python 0.01% Objective-C 0.01% Makefile 0.23% CartoCSS 0.01% Assembly 0.35%

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Hi there, I code just for fun 🚀

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