This project forked from jomonkjoy/axis-async-fifo
parameterized AXIS FIFO design
parameterized AXIS FIFO design
The top -level FIFO module is a parameterized FIFO design with all sub-blocks
instantiated using the recommended practice of doing named port connections.
Simulation and Synthesis Techniques for Asynchronous FIFO Design
Clifford E. Cummings, Sunburst Design, Inc.
[email protected]
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