iencinas10 / pa Goto Github PK

https://marz.utk.edu/my-courses/cosc230/book/example-risc-v-assembly-programs/#sum_of_an_integer_array

https://github.com/TheThirdOne/rars

• Make auipc instruction. "la" expands into two instructions, the auipc and an addi.. its not one or the other. It is BOTH (read carefully)

https://hackmd.io/@kaeteyaruyo/risc-v-hw1

Si googleas no tienes ni que pensar tu el codigo xd copypastea en el RARS, comprueba que funcionan gucci y usan unicamente nuestras instrucciones y au

• ROB/SB full condition
• Make ROB
• Make caches
• Hook stages (get datapath)
• Bypass unit

Ver que los vectores y las matrices esten alineadas si vamos a usar una direct mapped cache. mucho cuidado...

A las malas usar fully associative y au.

También: podemos modificar los programas para que hagan los 4 load word de la linea de cache en orden

PINEAR LINEAS PENDIENTES DE STORE (con un CONTADOR) si hay varios stores pendientes no podemos "unpinear" hasta que todos hayan acabado. CONTADORRRRRR

Lets fix the for loop to start from 1.

Current structure is:

F_D -> D_E -> E_M -> M_WB
-> M2_M3

We should fix that to

D_E -> E_M
-> M1_M2 (THIS WRITES BACK alu_result, alu_rob_wenable, alu_rob_id)

And fix stalls accordingly

Combinar esto
https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV#step-20-using-the-gnu-toolchain-to-compile-programs---assembly

Hacer un for loop que sea del estilo de:

initial begin
    $readmem("programa.o", MEM)
end

`UNIT_TEST("NOSE")
    for(int i = 0; i < NUM_INSTRUCCIONES_PROGRAMA; i++) {
        instr = MEM[i];
        #1
   }
`UNIT_TEST_END

Con los tests del decoder y comprobar que podemos leer instrucción a instrucción y que el decoder saca el resultado bien (menos el auipc ese de los cojones que aun no está)

https://www.chipverify.com/verilog/verilog-arrays-memories

• Mirar si podemos leer el "programa.o" con un "offset". Cuando metamos memoria virtual, PC virtual 0x0 leerá la dirección FISICA 0x8000. Si podemos "desplazar" todo el programa por un offset de 0x8000 estamos gucci
  Se hace con el linker script

Make 1 testbench for every test program and check that results are as expected when possible

• vectorCopy
• vectorSum
• matrixMul
• Extra

do:

inital valid = 0
end

https://www.chipverify.com/verilog/verilog-initial-block

For every stage and see if we can come out of reset correctly?

pa.odg

LB loads a byte and sign-extends it. So we can forward from the Store Buffer from a SW or a SB

LW can only be forwarded from a whole SW in the RB with a exact match.

• Split (ALU, MUL) and cache pipelines in order to avoid stalling (after exec stage), rework stalling logic...
• See which stages have to receive a RESET signal when exceptions occur¿? ALL

Example

arco-elpis.pdf

https://github.com/users/IEncinas10/projects/2/views/1

• ALU doesn't have exceptions. At most, we could signal overflow but we're not going to do anything with it anyway

• Also, "zero" signal is wrong

• Taking a branch is not an exception. We can simply set aluOut different to 0 if its taken and handle it in the execution stage

module execution stage..

assign branchTaken = aluOut != 0 && instr_J_type; 

We need to raise the reset signal in order to clean RF_ROB, but when doing so we're also resetting the register file.

We don't care too much because after exceptions we're going to get stuck in a loop, and we don't reset the store buffer