ricv-ml project contains FPGA prototype of functional RISCV core able to :

• run Linux rootfs build with riscv toolchain ( from SDCARD )
• connect to SDCARD core
• connect to DDR3
• connect to NVDLA core ( not tested )
• run nvdla driver on Linux ( not implemented )
• run ml projects ( not implemented )

RISCV core was generated with https://bar.eecs.berkeley.edu/projects/rocket_chip.html and was configured for RochetChip version with virtual memory , i$ and d$.

Github project for RocketChip : https://github.com/chipsalliance/rocket-chip/blob/master/README.md

Github project for NVDLA : https://github.com/nvdla

• gen_linux_img - steps to build Linux for RocketChip
• img - diagrams
• ip-cores - ip cores teste with RocketChip
• nvdla - rtl for NVIDIA Deep Learning Accelerator ( NOT connected to RocketChip )
• qmtech_board - Vivado board configuration
• vivado_proj - RocketChip project ( constraints & ip cores )

• board Qmtech Wukong :
  • fpga - XILINX XC7A100T ( 101,440 LC )
  • ddr3 - MICRON MT41K128M16JT-125:K, 256M
  • spi - S25FL128L,16M
  • eth - RealTek RTL8211EG
  • clk - 50 MHz

• EDA - Vivado/Vitis

• axi4-uart - AXI4 UART
• sdc - AXI4 SDC controller
• ddr3 - AXI4 Xilinx MIG / from Github project DDR

• README in folder gen_linux_img
  • Follow steps from github project fpga-rocket-chip
  • Append content of DTS file ( vivado_proj/bootrom.dts ) from step 1.3 Preparing the project

• Add wukong target to Vivado

• Project contains following components :

  • RocketChip cpu
  • DDR controller
  • IO : SPI & SDC & UART
  • PLL
  • BSCAN

• Generate project

  • cd /vivado_proj
  • vivado -mode batch -source riscv-ml.tcl

• Check memory address :

• Block Design :
• Top design is riscv-wrapper.v
• Generate bistream

• Check folder gen_linux_imgto build Linux and create sdcard
• Boot log :

• Project is NOT tested or connected to RocketChip
• linux driver - https://github.com/caihuoq/nvdla
• rtl - folder nvdla