Warnings by GoWin IDE about fx68k HOT 2 CLOSED

Hi Till,

Seems like a defect in the Verilog compiler you are using. Or at least a very particular interpretation of the language. I'm not an expert on the subtle details of the language. But in the second case it definitely seems like your compiler is broken. May be the compiler ignores the "unique" clause used in the case statement, or it doesn't support local variables?

reg type doesn't necessarily specific a latch or a register. It can be used in combinational logic. Actually in cases like this, reg (or logic) must be used and a wire declaration is not allowed.

Anyway, your modifications seems fine.

Regards,

Anyway,

from fx68k.

Hi Ijor. Thanks for the fast reply.

I am definitely no expert. But I think I understand why the tool complains (I am unsure, but IMHO under the hood it's Synopsis/sinplify). In both cases there are combinatorics which aren't set under all circumstances. So there are situations where the expected behavior seem to be to keep the current state. Which in turn is a latch.

Anyway. It works all and also the blitter works and I am actually pretty impressed that the code works out of the box on a synthesis tool it has never been tested for and which is not very mature.

Thanks again. I am having a lots of fun with your code ...

from fx68k.