How to request the bus? about fx68k HOT 6 CLOSED

Without a clock I can't tell but are you asserting BGACKn and deasserting BRn in the same cycle?

from fx68k.

Yes, the logic is like this:

always @(posedge clk, posedge rst)
    if( rst ) begin
        cpu_BRn    <= 1'b1;
        cpu_BGACKn <= 1'b1;
    end else begin
        casez( {cpu_BGACKn, cpu_BGn} )
            2'b11: // waiting for bus request
                if( |dev_br ) begin
                    cpu_BRn <= 1'b0;                    
                end
            2'b10: begin // bus granted
                cpu_BGACKn <= 1'b0;
                cpu_BRn    <= 1'b1;
            end
            2'b0?: // bus held by the device
                if( !(|dev_br) ) begin
                    cpu_BGACKn <= 1'b1; // frees the bus
                end
        endcase
    end

dev_br stands for device bus request. It is a bus signal made of all devices than request the bus.
Note that this block does not use clock enable signals, but maybe it should use the same clock enablers as fx68k.

from fx68k.

In the 68000 manual, Figure 5-15. 3-Wire Bus Arbitration Timing Diagram, asserting BGACKn and deasserting BRn doesn't happen in the same cycle. And section 5.2.3 Acknowledgement of Mastership says "The bus request from the granted device should be negated after BGACK is asserted."

from fx68k.

This is probably not the issue as Figure 5-20 has BGACKn asserting and BRn deasserting in the same cycle. @ijor will know for sure.

from fx68k.

I am waiting now for ASn to go high and that helps.

        casez( {cpu_BGACKn, cpu_BGn} )
            2'b11: // waiting for bus request
                if( |dev_br ) begin
                    cpu_BRn <= 1'b0;                    
                end
            2'b10: begin // bus granted
                if( cpu_ASn /*&& cpu_DTACKn*/ ) cpu_BGACKn <= 1'b0;
            end
            2'b0?: begin // bus held by the device
                cpu_BRn  <= 1'b1;
                if( !(|dev_br) ) begin
                    cpu_BGACKn <= 1'b1; // frees the bus
                end
            end
        endcase

Still, an old core stopped working after the change (Tiger Road)

from fx68k.

Hi Jose,

FX68K behaves as a real 68000 with the exception noted below.

You don't necessarily have to assert the signals at a specific cycle, the core performs an internal synchronization anyway. But the core, by default, does expect the signals to be asserted at the right phase of the clock. Otherwise, you need to uncomment a couple of lines at the source to preserve cycle accuracy (see the rBR register). If you don't assert the signals at the right phase and you don't uncomment those lines, it still shouldn't be fatal. The worst that should happen is that the core might grant the bus one cycle earlier than a real 68K. But this scenario wasn't extensively tested. I recommend asserting the signals at the "enPhi1" cycle.

Yes, it is imperative to wait until AS is deasserted. Depending on the case it might be necessary to wait for DTACK to be asserted as well. It is also necessary to not deassert BGACK (or BR) until the external master completed the bus cycle.

If there is only one master, BGACK can be asserted and BR deasserted at the same cycle. But if so you probably can use a 2-wire arbitration scheme that is much simpler than the 3-wire one. Just hold BGACK high all the time.

Note that depending on the platform, just following the bus protocol might not be enough. The software or the chipset might expect a specific timing of the bus master. Some systems delay BR or BGACK for a few cycles. I realize in some cases it is not available, but ideally you should follow traces taken on real hardware.

from fx68k.