The Cache Controller System-on-Chip (SoC) was designed, developed, and simulated on a Xilinx Spartan FPGA. The cache controller is a crucial component in a computer's memory hierarchy, managing the interaction between the CPU and the memory blocks (SRAM and SDRAM). The controller was implemented with VHDL within the Xilinx ISE CAD environment, and it cycles through various states of the designed state machine in response to read and write requests from the CPU, with each state transition triggered by the clock input.