This repository contains the implementation of a Universal Asynchronous Receiver/Transmitter (UART) module on a Field-Programmable Gate Array (FPGA) platform. The project was completed as part of the EN2111 - Electronic Circuit Design module at the Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.

• Fernando W.W.R.N.S.
• Gammune D.J.T.
• Herath H.M.S.I.

Special thanks to Lohan, Charels, and Kaveendra for their assistance in transferring and verifying the data.

The objective of this project is to design, implement, and verify a UART module on an FPGA, providing reliable asynchronous serial communication.

• 📡 UART protocol implementation
• 💻 FPGA-based design and verification
• 🔬 Comprehensive testbench development
• 🛠️ RTL code for transmitter and receiver
• 📊 ModelSim simulation and timing diagram analysis

The project is divided into four distinct phases:

• Research the UART protocol, including data framing, synchronization, and baud rate settings.
• Explore existing Verilog implementations of UART transceivers.
• Review and select a suitable implementation that meets the specified requirements.

• Understand the UART module's input and output signals.
• Write a Verilog testbench to simulate the UART environment.
• Test the UART module with various data patterns, baud rates, and edge cases.
• Utilize ModelSim for simulation and debugging.

• Set up the FPGA development environment (Intel Quartus).
• Develop additional RTL for driving the 7-segment displays.
• Simulate and verify the UART and 7-segment drive circuit.
• Integrate the UART RTL with FPGA specifics, such as GPIO pin assignments and clock frequency matching.
• Synthesize the design, perform place and route, and download the bitstream to the FPGA board.

• Set up an oscilloscope and connect probes to the UART TX and RX lines.
• Configure the oscilloscope for appropriate time and voltage settings.
• Transmit data from the FPGA and observe the waveform corresponding to the UART protocol.
• Analyze the signal for correct start bit, data bits, parity bit, stop bit, and potential signal integrity issues.

Hardware:

• FPGA development board (e.g., DE0 Nano)
• Oscilloscope (for signal analysis)

Software:

• Intel Quartus (for FPGA development)
• ModelSim (for simulation)

• RTL/: Contains the Verilog code for the UART implementation
  • uart.v: Top-level UART module
  • transmitter.v: UART transmitter module
  • receiver.v: UART receiver module
• Testbench/: Contains testbench files
  • testbench.v: Main testbench for UART
  • transmitter_tb.v: Testbench for transmitter
  • trans_rec_tb.v: Testbench for transmitter and receiver
• Docs/: Documentation files
  • Project_Report.pdf: Detailed project report
• Simulation/: ModelSim simulation files and results
• FPGA/: FPGA-specific files (pin assignments, etc.)

1. Clone the Repository:

git clone https://github.com/JayxTG/UART-FPGA-Implementation.git

2. RTL Implementation:

• Open the RTL files in the RTL/ directory to view or modify the UART implementation.

3. Simulation:

• Use ModelSim to run the testbenches in the Testbench/ directory.
• Analyze the timing diagrams and simulation results.

4. FPGA Implementation:

• Open the project in Intel Quartus.
• Synthesize the design and program the FPGA board.

5. Testing:

• Use the provided testbenches to verify functionality.
• For hardware testing, refer to the pin planner in the report for proper connections.

• Successful implementation of UART transmitter and receiver modules.
• Verified functionality through comprehensive testbenches and ModelSim simulations.
• Timing diagrams and pin planning available in the project report.

1. Implementation of UART Protocol Using FPGA
2. FPGA Basics (Intel)
3. UART: A Hardware Communication Protocol
4. UART-Implementation-Using-FPGA (GitHub)
5. DE0 Nano User Manual

This project is open-source and available under the MIT License.