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DDR3 controller for nMigen (WIP)

License: Other

Python 90.22% Makefile 0.28% C 3.48% Shell 0.71% Verilog 4.59% SystemVerilog 0.71%

ram ddr3 nmigen fpga ecp5 trellis

gram's Introduction

gram

gram is an nMigen+LambdaSoC port of the LiteDRAM core by enjoy-digital. It currently only targets ECP5+DDR3.

gram is a LambdaConcept project.

Requirements

nMigen + nMigen-SoC + LambdaSoC

gram requires nMigen >= 0.3.

License

2-clause BSD.

gram's People

Stargazers

Watchers

Forkers

mfkiwl

gram's Issues

Parallelize unit tests

https://pypi.org/project/unittest-parallel/

Write transactions aren't properly detected by the DRAM model

Simulation file: simsoc.zip

As you can see on the picture below, the bitmask used for saving things into RAM is completely empty:

It also seems like dq_in_* are empty at that point. This might be caused by DM/DQ signals arriving too early.

Generate MRx values according to DRAM chip specs

Currently we use hardcoded values of the MR registers that only work on the ECPIX-5. We should either:

set MR registers at compile time (leaner code, smaller ROM footprint)
allow loading MR registers from a struct of some sort (needs a bit more code but could allow for a single firmware image to work on multiple boards with different RAM chips)

Report software version in CI

We're currently doing CI builds with the master/main branch of:

nMigen
nMigen-SoC
LambdaSoC
Yosys
SymbiYosys
Icarus Verilog

We should have in the build log the version number or Git identifier of each software we're running.

Signal driven from multiple places

/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/core/refresher.py:209: DriverConflict: Signal '(sig done)' is driven from multiple fragments: top.dramcore.controller.refresher.zqs_executer, top.dramcore.controller.refresher.zqs_executer.<unnamed #0>; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/core/bankmachine.py:95: DriverConflict: Signal '(sig cmd__ready)' is driven from multiple fragments: top.dramcore.controller.multiplexer.choose_cmd, top.dramcore.controller.multiplexer.choose_req; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/core/bankmachine.py:95: DriverConflict: Signal '(sig cmd__ready)' is driven from multiple fragments: top.dramcore.controller.multiplexer.choose_cmd, top.dramcore.controller.multiplexer.choose_req; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/core/bankmachine.py:95: DriverConflict: Signal '(sig cmd__ready)' is driven from multiple fragments: top.dramcore.controller.multiplexer.choose_cmd, top.dramcore.controller.multiplexer.choose_req; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/core/bankmachine.py:95: DriverConflict: Signal '(sig cmd__ready)' is driven from multiple fragments: top.dramcore.controller.multiplexer.choose_cmd, top.dramcore.controller.multiplexer.choose_req; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/core/bankmachine.py:95: DriverConflict: Signal '(sig cmd__ready)' is driven from multiple fragments: top.dramcore.controller.multiplexer.choose_cmd, top.dramcore.controller.multiplexer.choose_req; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/core/bankmachine.py:95: DriverConflict: Signal '(sig cmd__ready)' is driven from multiple fragments: top.dramcore.controller.multiplexer.choose_cmd, top.dramcore.controller.multiplexer.choose_req; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/core/bankmachine.py:95: DriverConflict: Signal '(sig cmd__ready)' is driven from multiple fragments: top.dramcore.controller.multiplexer.choose_cmd, top.dramcore.controller.multiplexer.choose_req; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/core/bankmachine.py:95: DriverConflict: Signal '(sig cmd__ready)' is driven from multiple fragments: top.dramcore.controller.multiplexer.choose_cmd, top.dramcore.controller.multiplexer.choose_req; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/stream.py:60: DriverConflict: Signal '(sig sink__ready)' is driven from multiple fragments: top.dramcore.controller.<unnamed #2>, top.dramcore.controller.<unnamed #2>.<unnamed #3>; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/stream.py:60: DriverConflict: Signal '(sig sink__ready)' is driven from multiple fragments: top.dramcore.controller.<unnamed #3>, top.dramcore.controller.<unnamed #3>.<unnamed #3>; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/stream.py:60: DriverConflict: Signal '(sig sink__ready)' is driven from multiple fragments: top.dramcore.controller.<unnamed #4>, top.dramcore.controller.<unnamed #4>.<unnamed #3>; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/stream.py:60: DriverConflict: Signal '(sig sink__ready)' is driven from multiple fragments: top.dramcore.controller.<unnamed #5>, top.dramcore.controller.<unnamed #5>.<unnamed #3>; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/stream.py:60: DriverConflict: Signal '(sig sink__ready)' is driven from multiple fragments: top.dramcore.controller.<unnamed #6>, top.dramcore.controller.<unnamed #6>.<unnamed #3>; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/stream.py:60: DriverConflict: Signal '(sig sink__ready)' is driven from multiple fragments: top.dramcore.controller.<unnamed #7>, top.dramcore.controller.<unnamed #7>.<unnamed #3>; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/stream.py:60: DriverConflict: Signal '(sig sink__ready)' is driven from multiple fragments: top.dramcore.controller.<unnamed #8>, top.dramcore.controller.<unnamed #8>.<unnamed #3>; hierarchy will be flattened
/home/jeanthomas/.local/lib/python3.8/site-packages/gram-0.0.0-py3.8.egg/gram/stream.py:60: DriverConflict: Signal '(sig sink__ready)' is driven from multiple fragments: top.dramcore.controller.<unnamed #9>, top.dramcore.controller.<unnamed #9>.<unnamed #3>; hierarchy will be flattened

refresher.py
bankmachine.py

Long critical path between refresher and somewhere in controller

Info: Critical path report for clock '$glbnet$sysclk_clk' (posedge -> posedge):
Info: curr total
Info:  0.3  0.3  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_6_SLICE.Q1
Info:  0.8  1.1    Net dramcore.controller.refresher.zqcs_timer.count[24] budget 0.266000 ns (28,84) -> (28,84)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_6_SLICE.B0
Info:  0.1  1.2  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_6_SLICE.F0
Info:  0.8  2.0    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD[0] budget 0.266000 ns (28,84) -> (25,84)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.A1
Info:  0.2  2.2  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  2.2    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 budget 0.000000 ns (25,84) -> (25,84)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.1  2.4  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  0.0  2.4    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1 budget 0.000000 ns (25,84) -> (25,84)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_SLICE.FXB
Info:  0.1  2.5  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_SLICE.OFX1
Info:  1.0  3.5    Net dramcore.controller.multiplexer.trrdcon.ready_LUT4_C_Z_LUT4_Z_2_C_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_C_Z_PFUMX_ALUT_C0_LUT4_Z_D_LUT4_C_A_LUT4_Z_D[0] budget 0.266000 ns (25,84) -> (16,79)
Info:                Sink dramcore.controller.U$$6.trccon.ready_LUT4_D_Z_LUT4_Z_C_LUT4_B_Z_LUT4_Z_1_D_L6MUX21_SD_D1_PFUMX_Z_SLICE.D0
Info:  0.2  3.7  Source dramcore.controller.U$$6.trccon.ready_LUT4_D_Z_LUT4_Z_C_LUT4_B_Z_LUT4_Z_1_D_L6MUX21_SD_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  3.7    Net dramcore.controller.U$$6.trccon.ready_LUT4_D_Z_LUT4_Z_C_LUT4_B_Z_LUT4_Z_1_D_L6MUX21_SD_D1 budget 0.000000 ns (16,79) -> (16,79)
Info:                Sink dramcore.controller.U$$6.trccon.ready_LUT4_D_Z_LUT4_Z_C_LUT4_B_Z_LUT4_Z_1_D_L6MUX21_SD_D1_PFUMX_Z_SLICE.FXB
Info:  0.1  3.8  Source dramcore.controller.U$$6.trccon.ready_LUT4_D_Z_LUT4_Z_C_LUT4_B_Z_LUT4_Z_1_D_L6MUX21_SD_D1_PFUMX_Z_SLICE.OFX1
Info:  0.8  4.7    Net dramcore.controller.U$$6.trascon.ready_LUT4_D_Z[3] budget 0.266000 ns (16,79) -> (16,78)
Info:                Sink dramcore.controller.U$$6.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_SLICE.C1
Info:  0.2  4.9  Source dramcore.controller.U$$6.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_SLICE.OFX0
Info:  0.0  4.9    Net dramcore.controller.U$$6.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_Z budget 0.000000 ns (16,78) -> (16,78)
Info:                Sink dramcore.controller.U$$6.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_SLICE.FXB
Info:  0.1  5.1  Source dramcore.controller.U$$6.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_SLICE.OFX1
Info:  0.0  5.1    Net dramcore.controller.U$$6.U$$1.source__payload__we_LUT4_B_1_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z budget 0.000000 ns (16,78) -> (16,78)
Info:                Sink dramcore.controller.U$$6.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.FXA
Info:  0.1  5.2  Source dramcore.controller.U$$6.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.OFX1
Info:  0.9  6.1    Net dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] budget 0.354000 ns (16,78) -> (17,80)
Info:                Sink dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_SLICE.C0
Info:  0.1  6.2  Source dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_SLICE.F0
Info:  1.0  7.2    Net dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z[1] budget 0.354000 ns (17,80) -> (20,80)
Info:                Sink dramcore.controller.U$$2.U$$0.fifo.r_rdy_LUT4_D_1_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.B1
Info:  0.2  7.4  Source dramcore.controller.U$$2.U$$0.fifo.r_rdy_LUT4_D_1_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  7.4    Net dramcore.controller.U$$2.U$$0.fifo.r_rdy_LUT4_D_1_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1 budget 0.000000 ns (20,80) -> (20,80)
Info:                Sink dramcore.controller.U$$2.U$$0.fifo.r_rdy_LUT4_D_1_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.1  7.6  Source dramcore.controller.U$$2.U$$0.fifo.r_rdy_LUT4_D_1_Z_PFUMX_ALUT_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  1.7  9.3    Net dramcore.controller.U$$2.trccon.ready_LUT4_D_Z[4] budget 1.867000 ns (20,80) -> (25,65)
Info:                Sink dramcore.controller.U$$2.U$$0.fifo.r_en_LUT4_Z_SLICE.D0
Info:  0.1  9.4  Source dramcore.controller.U$$2.U$$0.fifo.r_en_LUT4_Z_SLICE.F0
Info:  1.1 10.5    Net dramcore.controller.U$$2.U$$0_source__ready budget 1.866000 ns (25,65) -> (23,61)
Info:                Sink dramcore.controller.U$$2.U$$0.fifo.storage.2.0.0$DPRAM1_SLICE.CE
Info:  0.0 10.5  Setup dramcore.controller.U$$2.U$$0.fifo.storage.2.0.0$DPRAM1_SLICE.CE
Info: 2.5 ns logic, 8.0 ns routing

DRAM is not responding to read requests

PHY issue: are we sending the right sequence?
DRAM model issue: is the model behaving correctly?

Burst detection is not working

Burst detection from DQSBUFM is always reporting no burst. This issue is both present in simulation and on hardware.

Use upstream platform file

We need to fix:

nmigen issue regarding diff pairs that use SSTL135D_I IO type (PR pending: amaranth-lang/amaranth#447)
nmigen or gram (or both?) issue regarding tristate IO and diff pairs

Add cti and bte to Wishbone frontend

Enabling burst readouts would enable us to get more performance out of the controller.

Add SymbiYosys to SourceHut builds

Currently our test suite fails because we haven't installed SymbiYosys.

Add more assertions to the CRG simulation

Ensure sync2x runs at 200 Mhz
Ensure sync runs at 100 Mhz
Ensure sync2x and sync are in... sync

max_time is never set to 1 when time counter is null (in Icarus Simulation)

Not sure why it's happening, as it has been formally verified with that specific spec (time = 0 <=> max_time = 1) in mind...

PyPI package name conflict

Turns out there is already a Python package named "gram":

[jeanthomas@computer gram]$ pip search gram
gram (0.2.1)                    - gram: GitHub Repo Account Manager

https://github.com/kawa-kokosowa/gram

Should we rename gram? Do messy things like naming the package nmigen-gram?

Remove old attrs in gramNativePort

Ensure the following can be removed:

# retro-compatibility # FIXME: remove
self.aw = self.address_width
self.dw = self.data_width
self.cd = self.clock_domain

Default to SEL=1 if SEL=0

PHY unit testing

The ECP5 DDR PHY relies on the following instances:

DDRDLLA
ODDRX2F
DQSBUFM
ODDRX2DQA
ODDRX2DQSB
TSHX2DQSA
BB
DELAYF
IDDRX2DQA
TSHX2DQA

In order to do simulation at the PHY level, we need to model the above instances.

Wishbone ack doesn't take rddata_valid into account

Just noticed that if I delay the rddata_valid signal, there is no repercution on the wishbone bus... Not sure yet if it's caused by the wishbone frontend or elsewhere.

Don't instantiate arbiters if there is only one master in crossbar

Currently we instantiate an arbiter for each bank even if there is only one master connected to the crossbar.

sel signal is buggy

https://builds.sr.ht/~macbook/job/271957

Critical path too long in dram core

Info: Critical path report for clock '$glbnet$sysclk_clk' (posedge -> posedge):
Info: curr total
Info:  0.4  0.4  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_4_SLICE.Q1
Info:  0.7  1.1    Net dramcore.controller.refresher.zqcs_timer.count[16] budget 0.197000 ns (21,92) -> (21,92)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_4_SLICE.A0
Info:  0.2  1.3  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD_LUT4_Z_4_SLICE.F0
Info:  1.0  2.3    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_SD[2] budget 0.197000 ns (21,92) -> (18,89)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.D1
Info:  0.3  2.6  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  2.6    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 budget 0.000000 ns (18,89) -> (18,89)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.2  2.8  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  0.0  2.8    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1 budget 0.000000 ns (18,89) -> (18,89)
Info:                Sink dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_SLICE.FXB
Info:  0.2  3.0  Source dramcore.controller.refresher.sequencer.count_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_SLICE.OFX1
Info:  1.3  4.2    Net dramcore.controller.refresher.sequencer.count_LUT4_C_Z[0] budget 0.196000 ns (18,89) -> (13,79)
Info:                Sink dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.D0
Info:  0.3  4.5  Source dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  4.5    Net dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1 budget 0.000000 ns (13,79) -> (13,79)
Info:                Sink dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.2  4.7  Source dramcore.controller.U$$0.row_opened_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  0.5  5.3    Net dramcore.controller.U$$0.row_opened_LUT4_D_1_Z[2] budget 0.196000 ns (13,79) -> (13,78)
Info:                Sink dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.D1
Info:  0.3  5.6  Source dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.OFX0
Info:  0.0  5.6    Net dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_Z budget 0.000000 ns (13,78) -> (13,78)
Info:                Sink dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXA
Info:  0.2  5.7  Source dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  0.0  5.7    Net dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_D_L6MUX21_Z_D1 budget 0.000000 ns (13,78) -> (13,78)
Info:                Sink dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.FXB
Info:  0.2  5.9  Source dramcore.controller.U$$0.U$$1.source__payload__we_LUT4_B_Z_PFUMX_ALUT_SLICE.OFX1
Info:  0.7  6.7    Net dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_3_D[3] budget 0.392000 ns (13,78) -> (16,77)
Info:                Sink dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_2_SLICE.D1
Info:  0.2  6.8  Source dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z_LUT4_Z_2_SLICE.F1
Info:  0.9  7.7    Net dramcore.controller.multiplexer.tccdcon.ready_LUT4_D_Z[1] budget 0.609000 ns (16,77) -> (16,80)
Info:                Sink dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.B1
Info:  0.3  8.0  Source dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX0
Info:  0.0  8.0    Net dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1 budget 0.000000 ns (16,80) -> (16,80)
Info:                Sink dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.FXB
Info:  0.2  8.2  Source dramcore.controller.U$$4.row_opened_TRELLIS_FF_Q_DI_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_SLICE.OFX1
Info:  1.3  9.5    Net dramcore.controller.U$$4.row_opened_LUT4_D_Z[3] budget 1.316000 ns (16,80) -> (16,89)
Info:                Sink dramcore.controller.U$$4.trccon.ready_LUT4_D_Z_LUT4_Z_SLICE.C1
Info:  0.2  9.7  Source dramcore.controller.U$$4.trccon.ready_LUT4_D_Z_LUT4_Z_SLICE.F1
Info:  0.9 10.6    Net dramcore.controller.U$$4.trccon.ready_TRELLIS_FF_Q_DI[3] budget 1.316000 ns (16,89) -> (16,90)
Info:                Sink dramcore.controller.U$$4.trascon.count_TRELLIS_FF_Q_2_DI_LUT4_Z_SLICE.D1
Info:  0.2 10.7  Source dramcore.controller.U$$4.trascon.count_TRELLIS_FF_Q_2_DI_LUT4_Z_SLICE.F1
Info:  0.6 11.3    Net dramcore.controller.U$$4.trascon.ready_TRELLIS_FF_Q_CE budget 1.316000 ns (16,90) -> (16,89)
Info:                Sink dramcore.controller.U$$4.trccon.ready_LUT4_D_Z_LUT4_Z_SLICE.CE
Info:  0.0 11.3  Setup dramcore.controller.U$$4.trccon.ready_LUT4_D_Z_LUT4_Z_SLICE.CE
Info: 3.4 ns logic, 7.9 ns routing

ERROR: Max frequency for clock         '$glbnet$sysclk_clk': 88.53 MHz (FAIL at 100.00 MHz)
Info: Max frequency for clock    '$glbnet$sysclk_init_clk': 306.47 MHz (PASS at 25.00 MHz)
ERROR: Max frequency for clock '$glbnet$sysclk_clk100_0__i': 99.42 MHz (FAIL at 100.00 MHz)

Info: Max delay <async>                            -> <async>                        : 0.98 ns
Info: Max delay posedge $glbnet$sysclk_clk         -> <async>                        : 5.48 ns
Info: Max delay posedge $glbnet$sysclk_clk100_0__i -> <async>                        : 9.60 ns
Info: Max delay posedge $glbnet$sysclk_clk100_0__i -> posedge $glbnet$sysclk_clk     : 9.75 ns
Info: Max delay posedge $glbnet$sysclk_clk100_0__i -> posedge $glbnet$sysclk_init_clk: 9.35 ns
Info: Max delay posedge $glbnet$sysclk_init_clk    -> <async>                        : 2.56 ns
Info: Max delay posedge $glbnet$sysclk_init_clk    -> posedge $glbnet$sysclk_clk     : 2.94 ns

Info: Slack histogram:
Info:  legend: * represents 18 endpoint(s)
Info:          + represents [1,18) endpoint(s)
Info: [ -1295,   2929) |************************************************************ 
Info: [  2929,   7153) |*************************+
Info: [  7153,  11377) |*********************+
Info: [ 11377,  15601) | 
Info: [ 15601,  19825) | 
Info: [ 19825,  24049) | 
Info: [ 24049,  28273) | 
Info: [ 28273,  32497) |+
Info: [ 32497,  36721) | 
Info: [ 36721,  40945) |*+
Info: [ 40945,  45169) | 
Info: [ 45169,  49393) | 
Info: [ 49393,  53617) | 
Info: [ 53617,  57841) | 
Info: [ 57841,  62065) | 
Info: [ 62065,  66289) | 
Info: [ 66289,  70513) | 
Info: [ 70513,  74737) |+
Info: [ 74737,  78961) |+
Info: [ 78961,  83185) |*+

Include CRG in gram

Should we include the CRG code in gram, or should it be written by the end-user?

ECP5 CRG is wonky

The current way of doing things is to use the PLL outside of its specs (ie. VCO=200Mhz, CLKOP divider=1, CLKFB=2). This should be avoided.

Wishbone DRAM content interface debugging

We can't currently run a memtest because the bus stalls when we do R/W accesses.

Informations:

gramWishbone's FSM stays in ~~Send-Cmd state~~ Wait-Write state

Externalize RoundRobin

Currently being discussed in nMigen: amaranth-lang/amaranth#448

Use dramsync as the default clock domain everywhere in gram

This avoids the presence of DomainRenamer in user code.

Customizable data width on wishbone frontend

The DRAM native port is 128-bit wide but we only have a 32-bit wishbone frontend. Having a 128-bit frontend would allow for more performance.

Use Up-Down converters from nmigen-soc

Could be used to replace the code migrated from LiteX, though currently a WIP: amaranth-lang/amaranth-soc#21

Bring back testing in gram

During the LiteDRAM -> dram I ditched all the simulation/test files. This is quite problematic, and should be addressed ASAP.

Ideas:

Formal verification whenever possible
Use SV models (Micron offers one)
- HowTo SV with FOSS tools? HowTo DDR I/O modeling for the ECP5?

ECP5DDRPHY is filled with "Case" statements but nMigen doesn't see anything wrong with it

The PHY is a submodule of the SoC

Sync data readout to DQSBUFM's datavalid

AXI frontend

Avoid usage of getattr

Getattr is omnipresent in LiteDRAM code and I think that it is generally a bad practice. We should use whenever possible arrays instead.

Memtest fail

Memtest is currently failing, investigation in progress.

Add ECP5 builds to SourceHut builds

This would allow to check automatically if the example gateware in examples/ can reach the desired operating frequency.

Use PinsN for RAS/CAS/WE

Boards descriptions in nmigen-boards seem to use PinsN description.

DQSBUFM not connected to top level

ERROR: DQSBUFM 'ddrphy.U$$25' DQSI input must be connected only to a top level input
ERROR: Packing design failed.

Fix bank activation failure

From simulation output:
simsoc.09072020.zip

simsoctb.ram_chip.reset at time 0.0 ps WARNING:         200 (actually 200) us is required before RST_N goes inactive.
simsoctb.ram_chip.cmd_task: at time 4167762500.0 ps INFO: Precharge Power Down Enter
simsoctb.ram_chip.cmd_task: at time 5535762500.0 ps ERROR: tPD maximum violation during Power Down Exit
simsoctb.ram_chip.cmd_task: at time 5535762500.0 ps INFO: Power Down Exit
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 CAS Write Latency =           5
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Dynamic ODT Rtt =          60 Ohm
simsoctb.ram_chip.cmd_task: at time 12979792500.0 ps INFO: Load Mode 3
simsoctb.ram_chip.cmd_task: at time 12979792500.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
simsoctb.ram_chip.cmd_task: at time 12979792500.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 DLL Enable = Enabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Output Drive Strength =          34 Ohm
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 ODT Rtt =          60 Ohm
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Additive Latency = 0
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Write Levelization = Disabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Qoff = Enabled
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Burst Length =  8
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Burst Order = Sequential
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 CAS Latency =           6
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Write Recovery =           5
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
simsoctb.ram_chip.cmd_task: at time 23397792500.0 ps INFO: ZQ        long = 1
simsoctb.ram_chip.cmd_task: at time 24810597500.0 ps INFO: Activate  bank 0 row 0000
simsoctb.ram_chip.cmd_task: at time 24810612500.0 ps WARNING: tDLLK violation during Read     .
simsoctb.ram_chip.cmd_task: at time 24810612500.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.cmd_task: at time 24810632500.0 ps WARNING: tDLLK violation during Read     .
simsoctb.ram_chip.cmd_task: at time 24810632500.0 ps INFO: Read      bank 0 col 008, auto precharge 0
simsoctb.ram_chip.data_task: at time 24810640000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = xxxx
simsoctb.ram_chip.data_task: at time 24810642500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = xxxx
simsoctb.ram_chip.data_task: at time 24810645000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = xxxx
simsoctb.ram_chip.data_task: at time 24810647500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = xxxx
simsoctb.ram_chip.data_task: at time 24810650000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = xxxx
simsoctb.ram_chip.data_task: at time 24810652500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = xxxx
simsoctb.ram_chip.data_task: at time 24810655000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = xxxx
simsoctb.ram_chip.data_task: at time 24810657500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = xxxx
simsoctb.ram_chip.data_task: at time 24810660000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = xxxx
simsoctb.ram_chip.data_task: at time 24810662500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = xxxx
simsoctb.ram_chip.data_task: at time 24810665000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = xxxx
simsoctb.ram_chip.data_task: at time 24810667500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = xxxx
simsoctb.ram_chip.data_task: at time 24810670000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = xxxx
simsoctb.ram_chip.data_task: at time 24810672500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = xxxx
simsoctb.ram_chip.data_task: at time 24810675000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = xxxx
simsoctb.ram_chip.data_task: at time 24810677500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = xxxx
simsoctb.ram_chip.cmd_task: at time 26031777500.0 ps ERROR: Activate  Failure.  Bank 0 must be Precharged.

ECP5 PHY signal lignes are invalid

For the "A" lines this is related to invalid data in "dfi.phases[0].address[i]"

Multi-driven signals in DFII

/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:258: DriverConflict: Signal '(sig dramcore_dfii_p0_rddata__w_data)' is driven from multiple fragments: top.dramcore.<unnamed #1>, top.dramcore.<unnamed #2>; hierarchy will be flattened
  elem = csr.Element(width, access, name=elem_name)
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:258: DriverConflict: Signal '(sig dramcore_dfii_p1_rddata__w_data)' is driven from multiple fragments: top.dramcore.<unnamed #1>, top.dramcore.<unnamed #2>; hierarchy will be flattened
  elem = csr.Element(width, access, name=elem_name)
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:258: DriverConflict: Signal '(sig dramcore_dfii_p0_rddata__w_data)' is driven from multiple fragments: top.dramcore.<unnamed #8>, top.dramcore.csr_mux_0; hierarchy will be flattened
  elem = csr.Element(width, access, name=elem_name)
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:258: DriverConflict: Signal '(sig dramcore_dfii_p1_rddata__w_data)' is driven from multiple fragments: top.dramcore.<unnamed #9>, top.dramcore.csr_mux_0; hierarchy will be flattened
  elem = csr.Element(width, access, name=elem_name)

Read issues after a write transaction

For some reason, the IDDR primitive doesn't work well for the second salve of 4 bits... The DELAYF primitive seems to work well.

Reliability issues when doing memtests

We are currently running into a reliability issue with the memtests:

The memtest fails whenever we introduce delay between the write and the read (this looks like a refresh issue and would be backed by #32)
The memtest fails when we want to read/write too much data => same as 1? or address slicer issue (or similar)?
Even if we don't fall into 1 or 2, we sometimes struggle to have a successful memtest

Timing violations reported by FakePHY

I implemented a basic Display construct for nMigen and finally got some output from the FakePHY display constructs:

[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d
[%016dps] RD->RD violation on bank %0d

There are currently three kinds of violations reported:

RD->RD
ACT->ACT
WR->WR

DQS group mismatch

ERROR: DQS group mismatch, port DQSW270 of 'ddrphy.U$$26' in group LDQ41 is driven by DQSBUFM 'ddrphy.U$$25' in group LDQ77
ERROR: Packing design failed.
0 warnings, 2 errors
Traceback (most recent call last):
  File "headless-ecpix5.py", line 240, in <module>
    platform.build(soc, do_program=True)
  File "/home/jeanthomas/.local/lib/python3.8/site-packages/nmigen/build/plat.py", line 94, in build
    products = plan.execute_local(build_dir)
  File "/home/jeanthomas/.local/lib/python3.8/site-packages/nmigen/build/run.py", line 95, in execute_local
    subprocess.check_call(["sh", "{}.sh".format(self.script)])
  File "/usr/lib64/python3.8/subprocess.py", line 364, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sh', 'build_top.sh']' returned non-zero exit status 255.

simsoctb.ram_chip.reset at time 0.0 ps WARNING:         200 (actually 200) us is required before RST_N goes inactive.
simsoctb.ram_chip.cmd_task: at time 4167762500.0 ps INFO: Precharge Power Down Enter
simsoctb.ram_chip.cmd_task: at time 5535762500.0 ps ERROR: tPD maximum violation during Power Down Exit
simsoctb.ram_chip.cmd_task: at time 5535762500.0 ps INFO: Power Down Exit
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 CAS Write Latency =           5
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Dynamic ODT Rtt =          60 Ohm
simsoctb.ram_chip.cmd_task: at time 12979792500.0 ps INFO: Load Mode 3
simsoctb.ram_chip.cmd_task: at time 12979792500.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
simsoctb.ram_chip.cmd_task: at time 12979792500.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 DLL Enable = Enabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Output Drive Strength =          34 Ohm
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 ODT Rtt =          60 Ohm
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Additive Latency = 0
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Write Levelization = Disabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Qoff = Enabled
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Burst Length =  8
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Burst Order = Sequential
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 CAS Latency =           6
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Write Recovery =           5
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
simsoctb.ram_chip.cmd_task: at time 23397792500.0 ps INFO: ZQ        long = 1
simsoctb.ram_chip.cmd_task: at time 24810597500.0 ps INFO: Activate  bank 0 row 0000
simsoctb.ram_chip.cmd_task: at time 24810612500.0 ps WARNING: tDLLK violation during Read     .
simsoctb.ram_chip.cmd_task: at time 24810612500.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.cmd_task: at time 24810632500.0 ps WARNING: tDLLK violation during Read     .
simsoctb.ram_chip.cmd_task: at time 24810632500.0 ps INFO: Read      bank 0 col 008, auto precharge 0
simsoctb.ram_chip.data_task: at time 24810640000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = xxxx
simsoctb.ram_chip.data_task: at time 24810642500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = xxxx
simsoctb.ram_chip.data_task: at time 24810645000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = xxxx
simsoctb.ram_chip.data_task: at time 24810647500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = xxxx
simsoctb.ram_chip.data_task: at time 24810650000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = xxxx
simsoctb.ram_chip.data_task: at time 24810652500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = xxxx
simsoctb.ram_chip.data_task: at time 24810655000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = xxxx
simsoctb.ram_chip.data_task: at time 24810657500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = xxxx
simsoctb.ram_chip.data_task: at time 24810660000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = xxxx
simsoctb.ram_chip.data_task: at time 24810662500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = xxxx
simsoctb.ram_chip.data_task: at time 24810665000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = xxxx
simsoctb.ram_chip.data_task: at time 24810667500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = xxxx
simsoctb.ram_chip.data_task: at time 24810670000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = xxxx
simsoctb.ram_chip.data_task: at time 24810672500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = xxxx
simsoctb.ram_chip.data_task: at time 24810675000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = xxxx
simsoctb.ram_chip.data_task: at time 24810677500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = xxxx
simsoctb.ram_chip.cmd_task: at time 26031777500.0 ps ERROR: Activate  Failure.  Bank 0 must be Precharged.

Fix unused Elaboratables

Logs from examples/ecpix5.py:

/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:182: UnusedElaboratable: <lambdasoc.periph.base.PeripheralBridge object at 0x7ff486db2af0> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:307: UnusedElaboratable: <nmigen_soc.wishbone.bus.Decoder object at 0x7ff486db2b50> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:331: UnusedElaboratable: <lambdasoc.periph.event.InterruptSource object at 0x7ff486db2b20> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:322: UnusedElaboratable: <nmigen_soc.csr.wishbone.WishboneCSRBridge object at 0x7ff486db2e80> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:316: UnusedElaboratable: <nmigen_soc.csr.bus.Multiplexer object at 0x7ff486db2c10> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:339: UnusedElaboratable: <nmigen_soc.csr.wishbone.WishboneCSRBridge object at 0x7ff486d3e8e0> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:334: UnusedElaboratable: <nmigen_soc.csr.bus.Multiplexer object at 0x7ff486d3e730> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:182: UnusedElaboratable: <lambdasoc.periph.base.PeripheralBridge object at 0x7ff486d00e50> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:307: UnusedElaboratable: <nmigen_soc.wishbone.bus.Decoder object at 0x7ff486d0d6a0> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:331: UnusedElaboratable: <lambdasoc.periph.event.InterruptSource object at 0x7ff486d00ee0> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:322: UnusedElaboratable: <nmigen_soc.csr.wishbone.WishboneCSRBridge object at 0x7ff486d0daf0> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:316: UnusedElaboratable: <nmigen_soc.csr.bus.Multiplexer object at 0x7ff486d0d760> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:339: UnusedElaboratable: <nmigen_soc.csr.wishbone.WishboneCSRBridge object at 0x7ff486d19550> created but never used
/home/jeanthomas/.local/lib/python3.8/site-packages/lambdasoc/periph/base.py:334: UnusedElaboratable: <nmigen_soc.csr.bus.Multiplexer object at 0x7ff486d193a0> created but never used

Limit the amount of exposed symbols in libgram

This is the output of nm for libgram.a:

init.o:
         U dfii_initseq
         U dfii_setsw
00000000 T gram_init

memtest.o:
00000000 T gram_memtest

dfii.o:
00000000 t cdelay
00000044 T dfii_initseq
00000010 T dfii_setsw
00000000 t .L2
00000024 t .L7

We currently only need to expose gram_init and gram_memtest.

Publish gram on PyPI

Dependency: #45