Fences that are strictly stronger than each other should contain both the strong and weak annotation. This makes reducing the tests straightforward.

E.g. when #Loc = #Thd = #Val = #E.

So it's a bit less verbose on the command line.

If the execution involves the following thread

    a:W x 1 -po-> b:W x 2 -po-> c:R x 2

(plus some other threads to make the execution inconsistent), and b is removed, then we end up with

    a:W x 1 -po-> c:R x 0

which is certainly inconsistent. This means that the original execution will not be considered minimally inconsistent. Need to consider extending rf with co.rf in rf. Or else leave rf edges unconstrained after removal.

So it can be invoked independently of the comparator executable.

Add a set of regression tests for the transactions branch.

In the litmus test below (produced from Allow set Power 6ev synthesis), we have 0:r1 being used as both the address of z and the destination register of the load of x. This in itself is not problematic if we can guarantee that the load of x will always occur. Since we always have a finite and small number of stores to x the litmus7 tool only needs a small buffer to store the possible values (say, 0,1,2).

However, this load of x is within a transaction, which can fail. In this case, 0:r1 will contain its initial value, the address of z. This will vary from run-to-run (since we explicitly use the stride feature of litmus7). If there are enough iterations where the transaction is rolled-back then we’ll collect a bunch of distinct addresses that eventually cause a segfault (due to the histogram collecting of litmus7 overflowing).

The fix is to ensure that that registers assigned for initial locations are disjoint from registers used within the postcondition.

PPC test_4e7901fedeee29511e054bb0aff3772c
{
ok = 1;
0:r1 = z;
1:r2 = z;
0:r4 = y;
1:r3 = y;
0:r5 = x;
1:r5 = x;
0:r7 = ok;
}
P0            | P1            ;
lwz r0, 0(r1) | li r1, 1      ;
cmpwi r0, 0   | stw r1, 0(r2) ;
bne Else00    | lwz r0, 0(r3) ;
Else00:       | cmpwi r0, 0   ;
tbegin.       | bne Else02    ;
beq TxnFail0  | Else02:       ;
li r3, 1      | li r4, 1      ;
stw r3, 0(r4) | stw r4, 0(r5) ;
cmpwi r0, 0   | Exit1:        ;
bne Else01    |               ;
Else01:       |               ;
lwz r1, 0(r5) |               ;
tend.         |               ;
b TxnSuccess0 |               ;
TxnFail0:     |               ;
li r6, 0      |               ;
stw r6, 0(r7) |               ;
b Exit0       |               ;
TxnSuccess0:  |               ;
Exit0:        |               ;

exists
(ok=1 /\ 0:r0=1 /\ 1:r0=1 /\ 0:r1=1 /\ x=1 /\ y=1 /\ z=1)

The following execution is synthesised for the allow-set for Power 6ev. It is inconsistent.

The execution was weakened from the following forbidden execution (by removing event e2).

Quoting John:

[...] it's a deadness issue.

An execution is minimally-interesting if it is interesting and any event-removal leads to an uninteresting execution.

An execution is interesting if it is inconsistent and dead.

When you remove E2, you get an inconsistent execution, but it's not dead, so it's deemed uninteresting.

The reason the reduced (i.e. 5-event) execution is not dead is because it has a ctrl dependency coming out of a read that observes the initial value. (You don't have this in the original 6-event execution.) Executions that have this pattern are deemed not dead. This, you may recall, was because I had an issue in POPL'17 whereby if I was control dependent on a read of zero, I couldn't tell if the read had successfully seen zero or just not happened yet. I'm no longer convinced that this is actually an issue.

The attached xml file (renamed to test.xml.txt) was generated with fences as nodes for PPC. This is problematic for our litmus generation:

$ ./gen -arch PPC -Tlit -o out.litmus test_10117.xml
Fatal error: exception Failure("Invalid fence attributes!")

The problem is the fence event. The function mk_fence for mk_ppc.ml expects an edge.

 let mk_fence attrs =
   match List.mem "sync" attrs,
         List.mem "lwsync" attrs,
         List.mem "isync" attrs with
   | true, false, false -> SYNC
   | false, true, false -> LWSYNC
   | false, false, true -> ISYNC
   | _ -> failwith "Invalid fence attributes!"

What's the right fix to deal with both cases? Should we lowercase attrs before doing the comparison?

out.pdf
test.xml.txt

MemAlloy assumes too much flexibility wrt offset-addressing for exclusives and acq/rel instructions. The "regular" LDR/STR instructions can take a base register and offset register, enabling us to create false address dependencies, like so:

LDR W0, [X1]
EOR W2,W0,W0
STR W3,[X4,W2,SXTW] ; address-dependence from load

The exclusive instructions LDXR/STXR and acq/rel instructions LDAR/STLR can't do this. They can only take a base register. So we must instead encode false address dependencies, like so:

LDR W0, [X1]
EOR W2,W0,W0
ADD W4,W4,W2
STLR W3,[X4] ; address-dependence from load

Add more regression tests to tests.sh. Include at least enough to reproduce all the results from the original POPL'17 paper.

Some SC-marked reads and writes are being emitted as non-atomic by mistake, which produces racy/undefined behaviour.

(Remind me to come back to this issue and fill it out with more detail!)

Investigate the use of Alloy's symmetry-breaking util/ordering on: S-order, co-order, then-order

It would be nice to be able to run 'gen' from a directory containing test directories (i.e. X_unique/) where X is a hash. There will also be a hashes.txt file inside the directory listing the hashes.