Odatix is a toolbox designed to facilitate logical synthesis of configurable designs on various FPGA and ASIC tools such as Vivado and Design Compiler. It allows to easily find the maximum operating frequency of any digital architecture described with an HDL (VHDL, Verilog, SystemVerilog, Chisel).

The primary feature of this toolbox lies in its capability to compare different architectural configurations using parameter files. With Odatix, users can effortlessly explore different architectural configurations and evaluate their performance based on numerous metrics including Fmax, hardware resource utilization, power consumption, and more.

Odatix also enables parallel simulations of different configurations of the same design. This is useful both for validation and for comparing configurations, as with benchmarks.

• Synthesis: Easily conduct logical synthesis on diverse FPGA and ASIC tools for various targets.
• Architecture Comparison: Easily compare architectural configurations using parameters.
• Fmax search: Find the maximum frequency of the design on a specific target.
• Simulation: Run simulations for each configuration of your design.
• Interactive Results Exploration: Visualize, compare, and explore architecture implementation results based on various metrics for each target.

Virtually any simulator! Check out the section Add your own simulation for more information.

Odatix includes examples for Verilator and GHDL.

• Installation
• Quick start
• Add your own design
• Add your own simulation
• Useful commands
• Settings documentation

For any inquiries or support, feel free to contact me at [email protected].

Note: Odatix is under active development, and we appreciate your feedback and contributions to make it even more powerful and user-friendly.