Design of a common source amplifier with active load using the skywater 130nm technology.

The following figures show the schematic of the circuit and the layout in MAGIC VLSI.

The design process will be as follows:

1. List project requirements;
2. List technology parameters given on https://skywater-pdk.readthedocs.io/en/main/index.html;
3. Find necessary parameters, such as $\lambda$ for the MOSFETs through graph analysis;
4. SPICE simulation of the circuit;
5. Check if it meets specifications;
6. Layout using MAGIC VSLI;
7. SPICE simulation post layout.

where $V_{th}$ is the threshold voltage, $\mu_0$ is the carrier mobility and $t_{ox}$ is the oxide thickness.

We also have $\epsilon_{rox} = 3.9$ and the vacuum electrical permitivitty is $\epsilon_0 = 8.8541 \cdot 10^{-12} \frac{F}{m}$. With that we can find $C_{ox}$,

For the pMOS: $$C_{ox} = \epsilon_0 \cdot \frac{\epsilon_{rox}}{t_{ox}} = 8.163\cdot 10^{-3} \frac{F}{m^2}$$ For the nMOS: $$C_{ox} = 8.325\cdot 10^{-3} \frac{F}{m^2} $$

Using 'lambda_n.spice' and 'lambda_p.spice', we found $$ \lambda_n = 0.038052 \ \frac{1}{V}$$ $$ \lambda_p = 0.069696 \ \frac{1}{V}$$

Now, in order to find the output resistance that meet the frequency response requirements, we can use $f_{pole} = \frac{f_u}{A_v}$, where $f_u$ is the unity gain bandwidth. So,

$$ R_o = \frac{1}{2\pi \cdot f_{pole} \cdot C_L} = 28.421 \ k\Omega$$

With this, we can find $I_{bias}$,

$$ I_{bias} = \frac{1}{(\lambda_n + \lambda_p)R_o} = 326.557 \ \mu A $$

And to satisfy the $V_{outmax}$ of the project parameters, the drain-source voltage of $M_2$ ($V_{DS2}$) must be 0.2 V ($V_{DD} - V_{outmax}$). Thus, the aspect ratio of $M_2$ ($M_3$ will have the same) is

$$ \left(\frac{W}{L}\right)_2 = \frac{2 \cdot I_{bias}}{\mu_{0p} \cdot C_{oxp} \cdot V_{DS2}^2} = 818.923 $$

Lastly, the aspect ratio of $M_1$ is calculated to provide the desired gain and minimum output voltage. Note that $g_m = \frac{A_v}{R_o}$.

$$\left(\frac{W}{L}\right)_1 = \frac{gm_1}{\mu_{0n} \cdot C_{oxn} \cdot (V_{GS1} - V_{thn})} = 69.985 $$

The DC simulation is used to find the operation voltage of the circuit.

We found 0.713 V. Using that voltage in the AC simulation we obtained the following plot.

The gain observed is 36.3636 dB, close to 40dB, in frequencies lower than 129.6 kHz. The cutoff frequency is about 1MHz and $f_u$ is 67.153 MHz, far from the 80 MHz wanted.

Finally, the transient analysis to see the behaviour of the amplifier with a small-signal input.

The table below summarizes the parameters obtained in the design before layout.

To use sky130 technology in MAGIC, we execute the software with the following line

magic -T sky130A.tech

Note that if the 'sky130A.tech' file is on a different directory we would have to do

magic -T ./directory/sky130A.tech

To install MAGIC and the necessary tools to design circuits with sky130 technology, check https://github.com/britovski/sky130_skel/.

The layout is shown below.

To see it better, open the mag file with MAGIC or the gds file with KLayout (or similar). I also uploaded a PDF version generated by KLayout.

Because the W values of the transistors were big, it was used the multi finger technique. Both PMOS gates were divided in 20 'fingers', so their width is

$$ W_{finger} = \frac{W}{n} = \frac{818.923 \mu m}{20} = 40.946 \mu m$$

For the NMOS, the division was made by 5

$$ W_{finger} = \frac{W}{n} = \frac{69.985 \mu m}{5} = 13.997 \mu m$$

Sequentially, the SPICE file was extracted using

extract all
ext2spice

The file is 'cs_amp_post_layout'. To be fair, the original file did not have the 'include' directives, nor the 'pshort_model.0' and 'nshort_model.0', instead it had 'pshort' and 'nshort', so this change was made to make it right.

Since it was used ports in MAGIC, it creates the SPICE file as a subckt. And it's worth noting that the ports sequence was different from the one used in the pre-layout SPICE file, so the testbench had a slight adjustment.

The DC simulation is shown in the following figure.

Here, we found a minor difference. The operation voltage was 0.713V and now it is 0.731V. Hence, using this voltage, we have the AC analysis.

The maximum DC gain is 36.1818 dB to frequencies under 151.513 kHz. The cutoff frequency obtained is 897.411 kHz (less than the expected, but closer to the specified one). The unity gain frequency is 56.89 MHz.

Lastly, the transient analysis.

We can conclude that the results collected were tolerable and the SPICE simulations before and after the layout were very similar.