It's a shame that such a great idea for a simple hdl parser which isn't tied into a larger bloatier package of tools and keeps within the simple scripting framework of the very popular scripting language python (does not require compiling as c++, more suitable for scripting, more widely used than perl) is no longer being actively maintained.

That being said, there are forks out there that are continuing the groundwork of this repo (it'd be nice if we could merge and move forward some of these ideas together so engineers aren't busy duplicating each other's work):

https://github.com/zhelnio/hdlparse (default parameter support, comments in parameters parsed correctly)
https://github.com/andresmanelli/hdlparse (I don't know much about vhdl, but seems this provides support for parsing entities).

Hello Kevin,

as GitHub hosts so many awesome lists (Python, Ruby, ...), I thought, we should create a list for VHDL too.

I created awesome-vhdl.
Please create a pull request and get hdlparse listed. You can also suggest to create or rename categories. When the number of listed VHDL projects increases, I'll create a PR for the awesome list itself (list of lists).

Looking forward to vote on your PR
Patrick

I tried hdlparse for parsing a small entity. The entity is known to be correct (used in many projects and working fine for synthesis and simulation). However, hdlparse just returns and empty list. Let me know how I can share the example code.

I checked the hdlparse code and obviously there is no handling for the action "entity" in the function "parse_vhdl()". Is this even implemented?

output logic [4:1] z, z2

Parsing above gives:
Ports:
logic output
4 output
1 output
z output
z2 output

hdlparse fails to match syntax like:

 component foo is
(...)
 end component foo;

patch
in vhdl_parser.py line 82

   (r'end\s+component\s*;', 'end_component', '#pop'),

substitute line with

   (r'end\s+component\s*\S*;', 'end_component', '#pop'),

Error in parsing the last Output in a module

module dut(

       input clk,rst,
       output reg [2:0]S1,
       output reg [2:0]S2,
       output reg [2:0]S3,
       output reg [2:0]S4
       );

Parsing the above code gives number of ports for S4 as 1.

In below case, the parser think "0", "Time", "1", and "Freq" are ports.
I don't know which line make it confuse.

To prevent that I added two "(r'/*', 'block_comment', 'block_comment')," to the parameter/moduel_port description of verilog_tokens.
Then it worked fine.

output reg Store_Type, /*0:Time, 1:Freq*/

always @(negedge rstb, posedge clk)
begin
if (!rstb) begin
Store_Ant <= 0;
Store_Sym <= 0;
Store_Type <= 0; /*0:Time, 1:Freq*/
Store_val <= 0;
end
else begin
...
end
end

This was the case I met.
input wire [29:0] input_data;

In that case, parser though that the port name is "_data".

lex.run(text)
in parse_verilog(text)
failed to correctly interpret portname that contain 'output' or 'input' as part of their name.

I could resolve this by adding word boundaries (\b) to the regexp in 'module' and 'module_port' (here lines 22 and 35, eg.:

  'module_port': [
    (r'\s*(input|inout|output)\b\s*(reg|supply0|sup...
                              ^^^

regards,
b.
;-)

I have a module which include a function in a module.
In that cases, it thought 'value' and 'lshift' are ports.

module xxx (
aaa
);

output reg [1:0] aaa;

function [29:0] lshift45_16;
input [44:0] value;
input [3:0] lshift;
begin
case (lshift)
8: lshift45_16 = {value[37: 8]};
9: lshift45_16 = {value[38: 9]};
10: lshift45_16 = {value[39:10]};
11: lshift45_16 = {value[40:11]};
12: lshift45_16 = {value[41:12]};
13: lshift45_16 = {value[42:13]};
14: lshift45_16 = {value[43:14]};
15: lshift45_16 = {value[44:15]};
default: lshift45_16 = value[44:15];
endcase
end
endfunction

endmodule

use_2to3 has been removed from setuptools after version 58. No longer builds nor gets installed via pip or otherwise. Breaks any projects that depend on it.
Users downgrading setuptools or making python3 version is the only solution.

If the maintainers are still active, someone can try making an MR which upgrades this to Python3. Or create a new fork Python3 instead otherwise.

Hello,

the github.io link to the documentation seems to be broken

So I saw in #3 that you are looking at trying to keep hdlparse simple and targeted at just being used for documentation generation.

In the IEEE Verilog 1364-2001 standard, an attribute is a way to add information to a Verilog object, statement or groups of statements that is tool-specific and does not affect simulation of that design. All Verilog-2001 attributes begin with the token (* and end with the token *). An attribute can be multi-line and is "attached" to the Verilog object, statement, or group of statements that is specified immediately beneath the attribute.

An example of an attribute is shown below;

(* preserve *) reg my_reg;

I think these attributes would be super useful to be included in documentation. In fact, I think you could probably use attributes for the "symbol-sections" inside Symbolator.

From reading the following page it seems fairly standard to support using attributes or special comment forms for specifying this type of special information. See below;

To use a synthesis attribute or directive in a Verilog Design File you can use the (* and *) delimiters. For example, you can use the following code to use the preserve synthesis attribute:

(* preserve *) reg my_reg;

You can also use a synthesis attribute or directive if you specify the synthesis attribute or directive in a comment in the file. The comment can use one of the following formats:

/* <comment> */
// <comment>

For example, you can use the following comment to use the preserve synthesis attribute in a Verilog Design File:

reg my_reg /* synthesis preserve */;

To use more than one synthesis attribute and/or directive for a single node, separate the synthesis attributes and/or directives with a space. For example, you can use the following comment to use the maxfan and preserve synthesis attributes for a single node:

reg my_reg /* synthesis maxfan = 16 preserve */;

Looking at this page these attributes can also be useful for adding more information about things like finite state machines;

 (* covered_fsm, channel, is="state", os="next_state",
                           trans="STATE_IDLE->STATE_IDLE",
                           trans="STATE_IDLE->STATE_HEAD",
                           trans="STATE_HEAD->STATE_DATA",
                           trans="STATE_HEAD->STATE_TAIL",
                           trans="STATE_DATA->STATE_DATA",
                           trans="STATE_DATA->STATE_TAIL",
                           trans="STATE_TAIL->STATE_HEAD",
                           trans="STATE_TAIL->STATE_IDLE" *)
  always @(reset or state or head or tail or valid)
    ...

Would you accept a patch which adds support for these?

Hi Kevin,

This is a good parser but it lacks a few things and since I am new to python I have struggled to make the necessary changes to fix these problems. I have used your examples to parse verilog and VHDL and here's what I have observed:

1. Verilog 95 style ports not supported
2. How do I print the parameter value - the example doesn't do it.
3. Support for multidimensional ports - barfs after the initial array type declaration. For example a port declared below cannot be parsed effectively.
   output logic [31:0][2:0] xyz
4. If parameters are declared as arrays like the following they cannot be understood:
   parameter ADDR_RANGE = 32'h00002000,
   parameter integer DATA_WIDTH_ARRAY [5:0] = '{64, 64, 64, 64, 64, 64},
5. Cannot print generics value in VHDL example provided.

Would it be difficult adding/fixing these features.

Thanks

NZ

Hello,

I am working on very similar project https://github.com/Nic30/hdlConvertor .
I am using parser/lexer generated from grammar written in ANTLR4 and representing HDL by json like objects.

Are you interested in cooperation?

Hi! I came across symbolator and hdlparse when I was looking to automate some of my documentation flow.
Is it possible that we can add Bluespec[1] support for hdlparse/symbolator ?
The Bluespec compiler already gives me verilog, but I think that parsing and diagramming Bluespec code will retain more high level information from my designs.

Please let me know if this is possible - I am willing to assist.

--
[1] : https://github.com/B-Lang-org/bsc

Entities and architectures can end with "end some_name;" instead of "end entity;" or "end architecture;" The regex should check for any word (maybe with \w) instead of the specific keywords "entity" and "architecture"

Hello, For a vhdl file like:

package example is
 CONSTANT MAX_NLBIST 		      : natural := 128;--changed from 16;
 CONSTANT MAX_NMCUT 		      : natural := 512;--changed from 96
 CONSTANT MAX_NRAM		      : natural := 512;--changed from 96
 CONSTANT MAX_NROM		      : natural := 512;--changed from 96

  component demo is
    generic (
      GENERIC1: boolean := false;
      GENERIC2: integer := 100
    );
    port (
      a, b : in std_ulogic := '1';
      c, d : out std_ulogic_vector(7 downto 0);
      e, f : inout unsigned(7 downto 0)
    );
  end component;
end package;

I wrote code to fetch the constants, But I am not getting anything. Could you please help.

import hdlparse.vhdl_parser as vhdl
from hdlparse.vhdl_parser import VhdlConstant
import io

vhdl_ex = vhdl.VhdlExtractor()
vhdl_consts = vhdl_ex.extract_objects('/home/nxf36037/example.vhd', VhdlConstant)



print('Component "{}":'.format(vhdl_consts))

The following code snippet in the documentation uses extract_objects_from_source when it should use extract_objects

import hdlparse.verilog_parser as vlog

vlog_ex = vlog.VerilogExtractor()
vlog_mods = vlog_ex.extract_objects_from_source('example.v')

for m in vlog_mods:
  print('Module "{}":'.format(m.name))

  print('  Parameters:')
  for p in m.generics:
    print('\t{:20}{:8}{}'.format(p.name, p.mode, p.data_type))

  print('  Ports:')
  for p in m.ports:
    print('\t{:20}{:8}{}'.format(p.name, p.mode, p.data_type))