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msvsd3bitfadc's Introduction

msvsd3bitfadc

Week 0

VSD - A complete guide to install open-source EDA tools

  1. Logic Synthesis
  2. Floorplanning
  3. Placement
  4. CTS
  5. Routing
  6. Static Timing Analysis at every stage CAD tools like magic help you visualize devices. Spice simulation ensures behavior. Already have running Ubuntu VM and required tools. Already installed magic and open_pdks. ALIGN
git clone https://github.com/ALIGN-analoglayout/ALIGN-public
cd ALIGN-public
python3 -m venv general
source general/bin/activate
python3 -m pip install pip --upgrade
# In general
source ~/ALIGN-public/general/bin/activate
pip install -v .
$ schematic2layout.py <NETLIST_DIR> -p <PDK_DIR> -c
$ mkdir work && cd work
$ schematic2layout.py ../examples/telescopic_ota -p ../pdks/FinFET14nm_Mock_PDK/
$ schematic2layout.py -h

ALIGN SKY130 libs

git clone https://github.com/ALIGN-analoglayout/ALIGN-pdk-sky130
$ schematic2layout.py <NETLIST_DIR> -p <PDK_DIR>
$ cd ALIGN-public
$ mkdir work && cd work
$ schematic2layout.py ../ALIGN-pdk-sky130/examples/five_transistor_ota -p ../ALIGN-pdk-sky130/SKY130_PDK/

Pre-layout Characterization for Inverter

Already finished in physical design workshop My repo Schematic Testbench Simulation

Post-layout Characterization for Inverter (Magic)

Setup Finished

extract do local
extract all
ext2spice lvs
//ext2spice cthresh 0.01 rthresh 0
ext2spice
netgen -batch lvs "../mag/inverter.spice inverter" "../xschem/inverter.spice inverter"

Netgen Magic Spice Magic Sim

Post-layout Characterization for Inverter (Align)

source ~/ALIGN-public/general/bin/activate
schematic2layout.py ../ALIGN-pdk-sky130/examples/five_transistor_ota -p ../ALIGN-pdk-sky130/SKY130_PDK/
magic -d XR
<read python.gds file>
<extract like above>
<label ports in out vdd vss>

Align Align Layout Align SPICE Align Sim

Week1

Fn Pre-layout

Pre-layout

ngspice fn_prelayout.cir
run
setplot tran1
plot out

ngspice post-ngspice

Fn Post-layout with Magic

Load

extract all
ext2spice

Spice Cap No ".option scale=0.125u" and has X (subcircuits) instead of M with more parasitic capacitances Multiplied all mag file rect dimensions due to incorrect sizing Fn Post Layout Netlist Simulation

Using Align instead of magic

Align Output Align Layout Spice Netlist Spice Simulation Spice Netlist Spice Simulation

Week2

cd
git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD.git
cd OpenROAD
./etc/DependencyInstaller.sh
cd
git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
cd OpenROAD-flow-scripts
./build_openroad.sh –local
export OPENROAD=~/OpenROAD-flow-scripts/tools/OpenROAD
export PATH=~/OpenROAD-flow-scripts/tools/install/OpenROAD/bin:~/OpenROAD-flow-scripts/tools/install/yosys/bin:~/OpenROAD-flow-scripts/tools/install/LSOracle/bin:$PATH

Header file in Klayout

Temperature Sensor Generation

HEADER file in Klayout SLC file in Klayout Make Done Results Before and After for Counter Openroad Flow Next Steps Floorplan Log Finished Report Finished GDS

Week3

Analog Schematic Analog Pre-layout Sim ALIGN flow utilized with diode connected MOSFETs and capacitors left out GDS files placed into corresponding folders. Align flow for counter analog files

Week4

New Ring Oscillator ADC Analog Sine Sim Analog Clock Sim Align Spice Ring Layout Ring Post Layout Spice Ring Post Layout Sim ADC Layout ADC Post Layout Include Spice ADC Post Layout Test Spice ADC Post Layout Sine Sim ADC Post Layout Ring Sim

Week5

Progress Update: unable to Complete OpenRoad flow in OpenFASOC Method: use existing infrasture of temp-sense-gen but replace file contents and comment/delete extraneous files Analog Modules Modify and Comment More Modifications

  • Renamed ring and adc gds/lef files to header and slc
  • Modified lef files for M(1-4) to met(1-4) Lef Progress Output Log

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