- Logic Synthesis
- Floorplanning
- Placement
- CTS
- Routing
- Static Timing Analysis at every stage CAD tools like magic help you visualize devices. Spice simulation ensures behavior. Already have running Ubuntu VM and required tools. Already installed magic and open_pdks. ALIGN
git clone https://github.com/ALIGN-analoglayout/ALIGN-public
cd ALIGN-public
python3 -m venv general
source general/bin/activate
python3 -m pip install pip --upgrade
# In general
source ~/ALIGN-public/general/bin/activate
pip install -v .
$ schematic2layout.py <NETLIST_DIR> -p <PDK_DIR> -c
$ mkdir work && cd work
$ schematic2layout.py ../examples/telescopic_ota -p ../pdks/FinFET14nm_Mock_PDK/
$ schematic2layout.py -h
git clone https://github.com/ALIGN-analoglayout/ALIGN-pdk-sky130
$ schematic2layout.py <NETLIST_DIR> -p <PDK_DIR>
$ cd ALIGN-public
$ mkdir work && cd work
$ schematic2layout.py ../ALIGN-pdk-sky130/examples/five_transistor_ota -p ../ALIGN-pdk-sky130/SKY130_PDK/
Already finished in physical design workshop My repo
extract do local
extract all
ext2spice lvs
//ext2spice cthresh 0.01 rthresh 0
ext2spice
netgen -batch lvs "../mag/inverter.spice inverter" "../xschem/inverter.spice inverter"
source ~/ALIGN-public/general/bin/activate
schematic2layout.py ../ALIGN-pdk-sky130/examples/five_transistor_ota -p ../ALIGN-pdk-sky130/SKY130_PDK/
magic -d XR
<read python.gds file>
<extract like above>
<label ports in out vdd vss>
ngspice fn_prelayout.cir
run
setplot tran1
plot out
extract all
ext2spice
No ".option scale=0.125u" and has X (subcircuits) instead of M with more parasitic capacitances Multiplied all mag file rect dimensions due to incorrect sizing
cd
git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD.git
cd OpenROAD
./etc/DependencyInstaller.sh
cd
git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
cd OpenROAD-flow-scripts
./build_openroad.sh –local
export OPENROAD=~/OpenROAD-flow-scripts/tools/OpenROAD
export PATH=~/OpenROAD-flow-scripts/tools/install/OpenROAD/bin:~/OpenROAD-flow-scripts/tools/install/yosys/bin:~/OpenROAD-flow-scripts/tools/install/LSOracle/bin:$PATH
ALIGN flow utilized with diode connected MOSFETs and capacitors left out GDS files placed into corresponding folders.
Progress Update: unable to Complete OpenRoad flow in OpenFASOC Method: use existing infrasture of temp-sense-gen but replace file contents and comment/delete extraneous files