This plugin simulates the panel layout of the eurorack-pmod FPGA-based module. See rtl/core.sv for the Verilog source. This example is intentionally kept as simple as possible.

1. Install VCV rack binaries or build it from source.
2. Install VCV rack SDK (or just put this folder in the plugins/ directory of Rack if you are building from source)
3. Install Verilator (used to build a C++ simulation from the Verilog core). You can either get it from your package manager or use the one included in the oss-cad-suite.

If you are using the SDK, make sure you have RACK_DIR set:

export RACK_DIR=<Rack SDK folder>

From the root directory of this repository:

$ make
$ make install

This plugin should now be visible on restarting VCV Rack.

At the moment only the audio rate sample_clk is injected into the verilog core, I doubt verilator would be fast enough to simulate filters pipelined at the PLL clock (12MHz/24MHz).