konstantinchizhov / mcucpp Goto Github PK

Do you plan to change requirements to python3?

Неверное имя файла:
mcucpp/MSP430/platform_dalay.h.
Правильнее будет platform_delay.h.

Орфоргафически неверное слово Cysles в именах постоянных.
Обьявление перечисления:
enum
{
PlatformCyslesPerDelayLoop32 = 4,
PlatformCyslesPerDelayLoop16 = 3,
PlatformCyslesPerDelayLoop8 = 3
};

Правильнее будет:
enum
{
PlatformCyclesPerDelayLoop32 = 4,
PlatformCyclesPerDelayLoop16 = 3,
PlatformCyclesPerDelayLoop8 = 3
};

RFM70 datasheet claims that only registers 0..8 from bank 1 should be written most significant byte first (MSB first).
Rfm70<>::WriteReg32() function writes 32-bit data in platform native endianess (little endian for AVR and STM32, not sure for MSP430). It means that Rfm70<>::WriteReg32() sends least significant byte of 32-bit word first.
But Rfm70<>::InitBank1Regs() assumes MSB first for WriteReg32(): "magic" register values from sample code for regs 0..6 are sent as-is, and only reg values for regs 0x0c and 0x0d send in reverse byte order.
Also SetAddresess() depends on WriteReg32() function and sets address incorrectly.

On STM32, it seems that unshifted port inversion mask applied to the shifted value upon PinRead() function. For example, if the following pin list used:
Pa1Inv, Pb2Inv, Pb3Inv, Pb4Inv, Pb5Inv, Pc10Inv, Pc11Inv, Pc12Inv,
it could be noted, that after read of PortC, value of three bits copied to the right position, then masked (we get 0xe0 in the case of all ones) and then inverted using 0x1c00 mask which is wrong and looks like unshifted PortC mask.

Compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.9.3 20150303 (release) [ARM/embedded-4_9-branch revision 221220]

I think in Mcucpp/mcucpp/AVR/adc.h on line 110:
ADCSRA = (ADCSRA & DividerMask) | divider;
should be:
ADCSRA = (ADCSRA & ~DividerMask) | divider;