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An open source FPGA miner for Blakecoin
An Open Source FPGA Blakecoin Miner This code is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. Project includes code from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner Also http://www.rcis.aist.go.jp/files/special/SASEBO/SHA3-ja/BLAKE.zip which quotes free license for research purposes, http://www.rcis.aist.go.jp/special/SASEBO/SHA3-en.html See https://bitcointalk.org/index.php?topic=306894.0 for forum discussion. Special thanks to fpgaminer for the original bitcoin mining code, teknohog for his serial code, also OrphanedGland, udif, TheSeven, makomk, and newMeat1 as credited on the fpgaminer bitcoin thread https://bitcointalk.org/index.php?topic=9047.0 and ngzhang for his Icarus/Lancelot boards and github. Not forgetting bluedragon747 for blakecoin! Ports are available for icarus/lancelot, ztex 1.15x, 1.15y and Cairnsmore CM1. The code currently achieves around 780MHash/s at 195Mhz on the lancelot board and around 1.5Gh/s on the quad boards (1.15y, CM1). All code is in the experimental folder and the bitstreams links for download are in bitstreams.txt All are supported by a modified cgminer 3.1.1 for use solo or on pool, there is also a python miner for the Icarus/Lancelot board (solo mining, or pool via getwork only).
All Ztex links are down (error 404). Can you upload bitstream for Ztex 1.15x fpga, please?
Bitstream https://www.dropbox.com/s/bbevqb8792emll9/CM1-hv-v04a-175MHz-ucf-150-fmax-161.bit
contained in the CM1 Readme.txt is 404 not found.
Please can you update with a recent link.
Hello Kramble. I am looking for someone to do some developing for a FPGA project for MaxCoin. I was told by the MAX devs that MAX is forked from Blakecoin and that you are a particularly talented programmer that might be able to help us out. Is there a way I can contact you privately about this issue without me posting my email? Thank you for your time.
There are 2 patches to cgminer of different versions.
They conflict to each other.
One patch to cgminer 3.1.1
FPGA-Blakecoin-Miner/cgminer/cgminer-3.1.1/driver-icarus.c says
`/* Blakecoin detection hash
N.B. golden_ob MUST take less time to calculate than the timeout set in icarus_open()
0000007002685447273026edebf62cf5e17454f35cc7b1f2da57caeb008cf4fb00000000dad683f2975c7e00a8088275099c69a3c589916aaa9c7c2501d136c1bf78422d5256fbaa1c01d9d1b48b4600000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000
{ midstate, data } = { 256'h553bf521cf6f816d21b2e3c660f29469f8b6ae935291176ef5dda6fe442ca6e4, 96'hd1d9011caafb56522d4278bf };
*/
const char golden_ob[] =
"553bf521cf6f816d21b2e3c660f29469"
"f8b6ae935291176ef5dda6fe442ca6e4"
"00000000000000000000000000000000"
"00000000d1d9011caafb56522d4278bf";
const char golden_nonce[] = "00468bb4";
const uint32_t golden_nonce_val = 0x00468bb4;
`
Another patch is for 3.4.3
FPGA-Blakecoin-Miner/cgminer/cgminer-3.4.3/driver-icarus.c
` /* Blakecoin detection hash
N.B. golden_ob MUST take less time to calculate than the timeout set in icarus_open()
0000007002685447273026edebf62cf5e17454f35cc7b1f2da57caeb008cf4fb00000000dad683f2975c7e00a8088275099c69a3c589916aaa9c7c2501d136c1bf78422d5256fbaa1c01d9d1b48b4600000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000
{ midstate, data } = { 256'h553bf521cf6f816d21b2e3c660f29469f8b6ae935291176ef5dda6fe442ca6e4, 96'hd1d9011caafb56522d4278bf };
*/
const char golden_ob[] =
"553bf521cf6f816d21b2e3c660f29469"
"f8b6ae935291176ef5dda6fe442ca6e4"
"00000000000000000000000000000000"
"00000000d1d9011caafb56522d4278bf";
const char golden_nonce[] = "000187a2";
const uint32_t golden_nonce_val = 0x000187a2;`
So SAME data in icarus detection code BUT DIFFERENT NONCES!!!!!!!
Which one is correct? Not clear.
MOST AWFUL that when those data are inserted into verilog testbench then board does not detect nonce!
LX150-Unrolled/test_blakeminer.v
Has a line for tested task
reg [415:0] data = 416'h000007ffffbd9207ffff001e11f35052d554469e3171e6831d493f45254964259bc31bade1b5bb1ae3c327bc54073d19f0ea633b;
And this task works properly in simulator ().
Also same line is used to set data directly into
FPGA-Blakecoin-Miner/experimental/LX150-Unrolled/serial.v
``ifdef SIM // Sane data for simulation - NB disable if simulating serial data loading
assign target = input_copy[415:384]; // Not needed since no RxD_data_ready strobe to load targetreg
assign data1 = 256'h3171e6831d493f45254964259bc31bade1b5bb1ae3c327bc54073d19f0ea633b; // midstate
assign data2 = 128'hffbd9207ffff001e11f35052d554469e; // NB ffbd9207 is loaded into nonce
// assign data2 = 128'hffbd9206ffff001e11f35052d554469e; // Test using prior nonce ffbd9206
else
BUT when midstate and data from cgminer C source inserted into testmench then simulator shows that board is not detected - NONCE NOT FOUND..
When midstate and data taken from generated FPGA-Blakecoin-Miner/MiningSoftware/testblakeminer.py
data - THEN verilog simulator shows that NONCE is FOUND properly.
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