Risc-V SoC Using LiteX

Build Risc-V SoCs Using LiteX framework

View License · LiteX Documentation · Report Bug · Request Feature

• About the Project
  • Tech Stack
  • Features
• Getting Started
  • Prerequisites
  • Installation
• License
• Contact
• Acknowledgements

• Use LiteX toolscain to quickly create an SoC and verify it.
• Use included Docker image to quickly install development enviroment
• Use included firmware files to program you SoC

• build - Folder includes Simulation\Verification files and build files for the gateware\software
• code - Folder includes the software demo files
• Docker Env - Folder includes the necessary files to build your Docker Development Environment
• docs - Folder includes SoC and peripheral documentation
• firmware - Folder includes firmaware files for the SoC
• micropython - Folder includes Micropython build experiment
• platform - Folder includes de10lite pins and quartus build options
• targets - Folder includes de10lite Base SoC peripheral build and programmer file
• software - Folder includes a helper scripts like a bitstream programmer

To run this project, you will need many environment variables added to your .env file and your O.S.Global Variables. Follow throught the wiki directions.

Start by reading litex wiki.

Python 3.10

 sudo apt-get install -y python3

Docker Installation

 sudo apt-get update

 sudo apt-get install \
    ca-certificates \
    curl \
    gnupg \
    lsb-release

sudo mkdir -p /etc/apt/keyrings &&
 curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /etc/apt/keyrings/docker.gpg

sudo apt-get install docker-ce docker-ce-cli containerd.io docker-compose-plugin

Folllow directions for troubleshooting https://tinyurl.com/2fpn3jt9

Clone the project

  git clone https://github.com/Lefteris-B/Risc-V-SoC-Using-LiteX.git

Make docker container

 cd Docker Dev Environment 

 make

or simply download the already made image :

 docker pull egbatzo/dipae-litex:latest

Use the docker image to build the development enviroment and create the elf binary files,uploadig the firmware, build gateware etc.

Please read the Code of Conduct

As part of this work, a SoC with RISC-V open-source architecture processor will be designed and developed using new synchronous design flow software. The target technology is Intel's FPGA technology provided by the laboratory. LiteX will be considered as a modern design stream, which is a SoC design stream and at the same time a HARDWARE IP library hosted on GitHub and providing utilities that can be used to create SoC in FPGA. LiteX IP components are described entirely using Python, which simplifies its design. LiteX already supports various soft processor cores as well as basic peripherals, without dependencies on closed source IP or code generators.

See LICENSE.txt for more information.

Lefteris D. Batzolis <egbatzo[at]teiemt[dot].gr>

Project Link: Risc-V-SoC-Using-Lite

SUBJECT AREA: Implementation of a RISC-V core with an FPGA. KEYWORDS: FPGA, LiteX, Python, RISC-V, SoC.

• LiteX
• DIPAE Website