lewiz-support / lmac_core1 Goto Github PK

Hi,

It seems to me that gmii_rx_dv is not used in LMAC_CORE_TOP module.

The following is my code trace:

LMAC_CORE_TOP(gmii_rx_dv) -> gige_rx(gmii_rx_dv) -> gige_s2p(gmii_rx_dv) -> END

Thanks!

Hi,

It seems to me that the line in AXIS_LMAC_TOP should use 'host_addr_reg_out' instead of 'host_addr_reg'; otherwise inside LMAC_CORE_TOP it will use host_addr_reg(from the 'clk' domain) under the 'gige_clk' domain.

Thank you.

Hi,
I have been trying to simulate the testbenches provided.
But getting the error message that I have attached the log file

I am using Intel FPGA starter edition of Modelsim 2021.1

I have tried with a differnet version of the modelsim. Modelsim SE version 64 10.7.
there it is showing the following error.

I am really looking forward to get support from @lewiz-support to guide me in this regard?
Thank you

An example which shows how to use the core on an FPGA board that I can purchase would be awesome. Some boards which would be awesome to support are;

• https://store.digilentinc.com/nexys-video-artix-7-fpga-trainer-board-for-multimedia-applications/
• https://store.digilentinc.com/genesys-2-kintex-7-fpga-development-board/

reg_rd_done in LMAC_CORE_TOP has multiple drivers coming from different clock domains

Hi,

I'm not sure if gmii_rxc is the clock source from the external PHY? If it is, then I'm not sure why gmii_rxc is used as data signal inside gige_s2p. Also, according to the code in gige_s2p, the gmii_rxc seems to be synchronous to the FMAC clock (125 MHZ). To my understanding, the FMAC clock source should be different from gmii_rxc, which comes from the external PHY.

Thanks!

Verilator is a super fast Verilog simulator. It would be good to have an out of the box ability to run the simulations with Verilator

It would be awesome for this core to support FuseSoC.

FuseSoC is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code.

Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.

@olofk can give you advice on how to do this

Hi, thank you for this open-source Ethernet Core Repo!

I have two questions about the GMII interface from LMAC_CORE_TOP.v.

1. For TX, to my understanding, the GMII interface usually has TX_ER signal, but it seems to me there's no signal related to it and I can only be able to find gmii_tx_vld, which I think does not belong to the standard TX GMII interface (TXD, TXC, TX_EN, TX_ER). Does gmii_tx_vld is actually the TX_ER signal?

2. For RX, the GMII interface from LMAC_CORE_TOP does not include RX_ER. This should be part of the GMII standard as well. Not sure if I have missed something or there's actually a reason to skip the RX_ER signal in LMAC_CORE_TOP?

Thank you very much!

Apparently you already have support for IP-XACT but it was not included in the contract release. It would be great if this could be added.