luckyebuka / arithmetic-and-logical-unit-alu- Goto Github PK
View Code? Open in Web Editor NEWThe design and implementation of an arithmetic logic unit (ALU) in VHDL (VHSIC Hardware Description Language) allow a variety of operations, including addition, subtraction, logical NOT, bitwise AND, bitwise OR, shifting, and others. This paper provides details on the design process, the VHDL code, and the testbench used for simulation.